Peripheral circuits of electrically programmable three-dimensional memory
OwnerGuobiao Zhanginventor
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Abstract
The present invention makes improvements to the peripheral circuits of the electrically programmable three-dimensional memory (EP-3DM). Full-read mode and self-timing are used to improve the speed and lower the power consumption. Cached EP-3DM is disclosed to reduce the latency. Redundancy can be employed to improve the yield of the EP-3DM.
Claims20
An electrically programmable three-dimensional memory (EP-3DM), comprising a substrate circuit, said substrate circuit comprising a peripheral circuit, said peripheral circuit further comprising a plurality of data sense-amplifiers (S/A);
- at least an EP-3DM level stacked on said substrate circuit, said EP-3DM level comprising a unit array, said unit array further comprising a plurality of EP-3DM cells, data-bit lines and data-word lines;
- a plurality of inter-level connecting vias, said inter-level connecting vias connecting said data-bit line with said data S/A.
An electrically programmable three-dimensional cached memory (EP-3DcM), comprising
- a substrate circuit, said substrate circuit comprising a peripheral circuit, an embedded RAM (eRAM) and a control block;
- at least an electrically programmable three-dimensional memory (EP-3DM) level stacked on said substrate circuit, said EP-3DM level comprising a plurality of EP-3DM cells and address-selection fines, said EP-3DM level using said peripheral circuit for address decoding and data sensing;
- a plurality of inter-level connecting vias, said inter-level connecting vias connecting said EP-3DM level with said peripheral circuit;
- wherein, the output of said peripheral circuit is connected with said eRAM, and said control block controls the data flow between said EP-3DM level and said eRAM.
An electrically programmable three-dimensional memory (EP-3DM), comprising
- a substrate circuit, said substrate circuit comprising an embedded ROM (eROM) and a plurality of multiplexors;
- at least an electrically programmable three-dimensional memory (EP-3DM) level stacked on said substrate circuit, said EP-3DM level comprising at least a defective structure selected from a defective EP-3DM cell, a defective word line and a defective bit line;
- a plurality of inter-level connecting vias, said inter-level connecting vias connecting said EP-3DM level with said substrate circuit;
- wherein, the output for said EP-3DM is selected from said EP-3DM level and said eROM by said multiplexors.
Dependencies are inferred from the claim text.