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US 2004/0016953 A1Published application
Three dimensional flash cell
AssigneeMicron Technology, Inc.
InventorsRoger W. Lindsay, Lyle Jones
Life of this patent
Estimating the term…
Abstract
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
Claims29
A memory cell, comprising:
- a substrate;
- source and drain regions located in the substrate and vertically spaced apart to define a channel region;
- a floating gate located adjacent the channel region, the floating gate extending substantially vertically;
- a control gate located adjacent to the floating gate;
- and
- wherein the control gate is coupled to a word line, the word line extending substantially parallel to the control gate in a horizontal direction.
3 more elements
A memory cell, comprising:
- a substrate having a pillar of semiconductive material;
- two source regions and a drain region formed in the substrate, the source and drain regions substantially vertically separated, and defining a first channel between the first source region and the drain region and a second channel between the second source region and the drain region, the source regions on opposite sides of the substrate pillar;
- a first floating gate structure adjacent the first channel, formed in a substantially vertical orientation;
- a first control gate structure adjacent the first floating gate, formed in a substantially vertical orientation;
- a second floating gate structure adjacent the second channel, formed in a substantially vertical orientation;
- and
- a second control gate structure adjacent the second floating gate, formed in a substantially vertical orientation
4 more elements
An array of memory cells, comprising:
- a plurality of rows of cells, each cell isolated from an adjacent cell by an isolation region within its row;
- and
- each row of cells having its cells staggered from cells in adjacent rows;
- wherein each cell comprises:
- a substrate;
- source and drain regions located in the substrate and vertically spaced apart to define a channel region;
- a floating gate located adjacent the channel region, the floating gate extending substantially vertically;
- a control gate located adjacent to the floating gate;
- and
- a plurality of word lines, each word line contacting a plurality of control gates in a row of cells, wherein each word line is substantially parallel to the control gates.
7 more elements
A non-volatile memory array, comprising:
- a substrate having a pillar of semiconductive material;
- a first memory cell, comprising:
- a drain region and a first source region in the substrate, the drain region and first source region substantially vertically separated to define a first channel therebetween;
- a first floating gate structure adjacent the first channel, formed in a substantially vertical orientation;
- and
- a first control gate structure adjacent the first floating gate, formed in a substantially vertical orientation;
- and
- a second memory cell, comprising:
- the drain region and a second source region in the substrate, the drain region and second source region substantially vertically separated to define a second channel therebetween;
- a second floating gate structure adjacent the second channel, formed in a substantially vertical orientation;
- and
- a second control gate structure adjacent the second floating gate, formed in a substantially vertical orientation.
9 more elements
An array of memory cells, comprising:
- a plurality of rows of memory cell pillars each pillar having a pair of memory cells formed thereon, each memory cell pillar isolated from an adjacent memory cell pillar by an isolation region within its row;
- and
- each row of pillars having its pillars staggered from pillars of adjacent rows of pillars to stagger adjacent memory cells;
- wherein each memory cell pillar comprises:
- a substrate;
- two source regions and one drain region, the drain region vertically spaced apart from the source regions to define two separate channel regions;
- a floating gate located adjacent each channel region, each floating gate extending substantially vertically;
- and
- a control gate located adjacent to each floating gate.
6 more elements
A method of fabricating a floating gate transistor comprising:
- fabricating a pillar of substrate material;
- fabricating vertically spaced source and drain regions to define a channel therebetween;
- fabricating a first layer of oxide over the channel;
- fabricating a substantially vertically configured semiconductive floating gate structure over the first layer of oxide and adjacent to the channel;
- fabricating a second oxide layer over the floating gate structure;
- fabricating a control gate structure over the second layer of oxide;
- and
- fabricating a horizontally extending word line coupled to the control gate structure, the word line contact extending substantially parallel to the control gate structure.
5 more elements
A method of fabricating a pair of floating gate transistors, comprising:
- fabricating a pillar of substrate material;
- fabricating first and second source regions and a drain region, each source region spaced apart vertically from the drain region to define a first channel between the first source region and the drain region and a second channel between the second source region and the drain region;
- fabricating a first layer of oxide over the channels;
- fabricating first and second substantially vertically configured semiconductive floating gate structures over the first layer of oxide and adjacent to the channels;
- fabricating a second oxide layer over the floating gate structures;
- fabricating first and second control gate structures over the second layer of oxide adjacent the first and second floating gates;
- and
- fabricating first and second horizontally extending word lines coupled to the first and second control gate structures, each word line contact extending substantially parallel to its control gate structure.
5 more elements
A method of fabricating a memory array, comprising:
- fabricating rows of memory cells on pillars separated by isolation regions therebetween, each pillar having a pair of memory cells, each on an opposite side thereof, and each row of memory cells having its cells staggered from cells in an adjacent tow of cells;
- fabricating control gates substantially between the rows of memory cells, each control gate to control half the cells of each of its adjacent rows of memory cells;
- and
- fabricating word lines for the array, the word lines extending substantially parallel to the control gates for the cells, each word line having contacts for memory cells in adjacent rows of the array.
1 more element
A flash memory device comprising:
- an array of floating gate memory cells arranged in rows having a staggered pattern of cells between adjacent rows of the device;
- and
- control circuitry to read, write and erase the floating gate memory cells, each memory cell comprising:
- a substrate;
- source and drain regions located in the substrate and vertically spaced apart to define a channel region;
- a floating gate located adjacent the channel region, the floating gate extending substantially vertically;
- and
- a control gate located adjacent to the floating gate.
5 more elements
A non-volatile memory comprising:
- a substrate;
- an array of non-volatile memory cells, wherein each memory cell comprises:
- source and drain regions located in the substrate and vertically spaced apart to define a vertical channel region;
- a floating gate located horizontally adjacent the channel region;
- a control gate located adjacent to the floating gate and extending in substantially vertically;
- a word line coupled to the control gate, wherein the word line extends in a direction parallel to the control gate;
- and
- control circuitry to program and read the memory cells.
5 more elements
A non-volatile memory array comprising:
- a first non-volatile memory cell comprising a source region and a first drain regions vertically spaced apart to define a first vertical channel region, and a first floating gate located lateral the first channel region;
- a second non-volatile memory cell comprising the source region and a second drain region vertically spaced apart to define a second vertical channel region, and a second floating gate located lateral to the second channel region;
- a control gate laterally located between the first and second floating gates;
- and
- a word line coupled to the control gate to control the first and second nonvolatile memory cells, wherein the word line extends in a horizontal direction generally parallel to the control gate.
2 more elements
A non-volatile memory array, comprising:
- a substrate having a pillar of semiconductive material;
- a first memory cell on a first side of the pillar, comprising:
- a drain region and a first source region in the substrate, the drain region and first source region substantially vertically separated to define a first channel therebetween;
- a first floating gate structure adjacent the first channel, formed in a substantially vertical orientation;
- and
- a first control gate structure adjacent the first floating gate, formed in a substantially vertical orientation;
- a first word line coupled to the first control gate, the first word line extending substantially parallel to the first control gate;
- and
- a second memory cell on a second side of the pillar opposite the first side, comprising:
- the drain region and a second source region in the substrate, the drain region and second source region substantially vertically separated to define a second channel therebetween;
- a second floating gate structure adjacent the second channel, formed in a substantially vertical orientation;
- a second control gate structure adjacent the second floating gate, formed in a substantially vertical orientation;
- and
- a second word line coupled to the second control gate, the second word line extending substantially parallel to the second control gate.
11 more elements
Dependencies are inferred from the claim text.