Integrated decoupling capacitors
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
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Abstract
A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.
Claims161
A method of forming a capacitor structure comprising:
- forming an opening in a doped semiconductor substrate which contains fin-like spacers extending from a bottom surface of said opening and formed of a doped semiconductor material;
- forming a dielectric material layer over the spacers;
- and
- forming an electrode material layer over the dielectric material.
A method of forming a capacitor in an integrated circuit comprising:
- forming an opening in a doped semiconductor substrate which contains supports of a doped semiconductor material;
- forming a dielectric material layer over said supports;
- forming an electrode material layer over said dielectric material;
- said capacitor being a decoupling capacitor within said integrated circuit.
A method of fabricating a capacitor in an integrated circuit comprising:
- forming an opening within a doped semiconductor substrate, said substrate opening containing microstructures formed of a doped semiconductor material;
- forming a dielectric material over said microstructures;
- forming an electrode material over said dielectric material;
- and
- forming integrated circuit components over said insulative material.
A method of reducing noise in an integrated circuit comprising:
- providing a doped semiconductor substrate;
- forming a capacitor that is recessed within said substrate, forming semiconductor components over said substrate, said components including a voltage line;
- and
- forming an electrical connection between said capacitor and said voltage line.
An integrated circuit comprising:
- a doped semiconductor substrate having an opening therein containing fin-like spacers formed of a doped semiconductor material;
- a dielectric material formed over said spacers;
- an electrode material formed over said dielectric material;
- and
- an insulating material formed over said electrode material.
A computer system comprising:
- a processor;
- and
- a memory device coupled to said processor, at least one of said processor and memory device containing a capacitor comprising:
- a substrate having an opening therein containing fin-like spacers formed of a doped semi-conductor material, a dielectric material formed over said spacers, and an electrode material formed over said dielectric material.
A capacitor structure comprising:
- a doped semiconductor substrate having a circular opening therein;
- doped semiconductor microstructures formed in a fan-like pattern about a center of said circular opening;
- a dielectric material over said microstructures;
- and
- an electrode material over said dielectric material.
Dependencies are inferred from the claim text.