System and method to improve IC fabrication through selective fusing
AssigneeTexas Instruments Incorporated
InventorsLeland Swanson, Gregory E. Howard
Life of this patent
Estimating the term…
Abstract
A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the performance capabilities of associated ICs. One or more respective parameters for unmeasured die are derived based on one or more of the measured parameter. Fuses are selectively set for ICs at each die location based on parameters associated with each respective die location, thereby configuring the respective ICs accordingly.
Claims28
A method to facilitate fabricating integrated circuits (ICs) on a wafer having a plurality of die locations comprising:
- measuring at least one respective parameter at a subset of the plurality of die locations on the wafer;
- determining at least one respective parameter for unmeasured die locations on the wafer based at least in part on at least one of the measured parameters associated with at least one of the subset of die locations;
- and
- selectively setting fuses for the plurality of die locations based on at least one of the respective parameters for the respective plurality of die locations to selectively configure ICs at each respective die location.
The method of claim 5, the respective impedance being computed for each die locations based on the circuit configuration of the ICs so as to provide desired IC performance.
A method to facilitate manufacture of integrated circuits (ICs) fabricated on a wafer comprising:
- measuring electrical characteristics associated with at least some of a plurality of die locations on the wafer, die locations at which the electrical characteristics are not measured defining unmeasured die locations;
- computing at least one respective parameter value for at least some of the measured die locations based on at least some of the electrical characteristics measured at the respective die locations;
- determining at least one respective parameter value for at least some of the unmeasured die locations based on the at least one parameter value computed for at least one of the measured die locations;
- and
- selectively setting fuses at each of the plurality of die locations based on at least one of the parameter values for each respective die location to configure ICs at each respective die location.
A method for compensating for variations in parameters across a wafer, which variations can affect performance characteristics of integrated circuits (ICs) fabricated at a plurality of die locations on the wafer, the method comprising:
- selectively setting fuses for at least a substantial portion of the plurality of die locations to configure the ICs associated with such die locations based on parameters determined for each of the respective substantial portion of the plurality of die locations from measurements taken for a subset of the die locations.
A system that facilitates fabrication of integrated circuits (ICs) on a wafer having a plurality of die comprising:
- a measurement system that measures at least one parameter at a subset of the plurality of die, the subset of die being spaced apart from each other across the wafer;
- at least one respective parameter associated with unmeasured die being determined based at least in part on the parameter measured for at least one die of the subset of die;
- and
- a fuse system that selectively sets fuses for at least a substantial portion of the plurality of die to configure respective ICs based on the parameter values at the measured and unmeasured die locations.
Dependencies are inferred from the claim text.