Power grid and bump pattern with reduced inductance and resistance
AssigneeSun Microsystems, Inc.
InventorsNayon Tomsio, Steven A. Schmidt, Linda S. Whitney
Life of this patent
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AssigneeSun Microsystems, Inc.
InventorsNayon Tomsio, Steven A. Schmidt, Linda S. Whitney
Estimating the term…
Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.
An apparatus comprising:
A method of providing an efficient pump structure, the method comprising:
Dependencies are inferred from the claim text.