Method of manufacturing a semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device comprising the following steps of:

• (a) forming a first p-well, a second p-well, a first n-well and a second n-well to a main surface of a semiconductor substrate, then forming a first gate insulative film to the surface for each of the first p-well and the n-well, respectively, and forming a second gate insulative film having a thickness larger than that of the first gate insulative film to the surface for each of the second p-well and the second n-well,
• (b) applying a heat treatment to the semiconductor substrate in an atmosphere containing nitrogen, thereby forming a first nitridation region having a first nitrogen concentration to the boundary between the second p-well and the second gate insulative film and to the boundary between the second n-well and the second gate insulative film, and forming a second nitridation region having a second nitrogen concentration higher than the first nitrogen concentration to the boundary between the first p-well and the first gate insulative film and to the boundary between the first n-well and the first gate insulative film,
• (c) depositing a silicon film on the semiconductor substrate, then forming a first photoresist film above each of the first n-well and the second n-well, then ion implanting n-impurities to the silicon film above each of the first p-well, and the second p-well thereby forming a n-silicon film,
• (d) ion implanting nitrogen through the n-silicon film to the first p-well and the second p-well while leaving the first photoresist above each of the first n-well and the second n-well, thereby
• forming a third nitridation region containing nitrogen in the first nitridation region as a portion thereof and having a third nitrogen concentration higher than the second nitrogen concentration to the boundary between the second p-well and the second gate insulative film, and
• forming a fourth nitridation region containing nitrogen in the second nitridation region as a portion thereof and having a fourth nitrogen concentration higher than the third nitrogen concentration to the boundary between the first p-well and the first gate insulative film,
• (e) forming a second photoresist film above each of the first p-well and the second p-well and forming a p-silicon film by ion implanting p-impurities to the silicon film above each of the first n-well and the second n-well,
• (f) patterning each of the n-silicon film and p-silicon film, thereby forming an n-semiconductor piece comprising the n-silicon film above each of the first p-well and the second p-well, and forming a p-semiconductor piece comprising the p-silicon film above each of the first n-well and the second n-well,
• (g) forming a third photoresist film above each of the first p-well, the first n-well and the second n-well, after the step (f) above, and ion implanting n-impurities to the second p-well, thereby forming an n-semiconductor region constituting a portion of source and drain in the second p-well,
• (h) ion implanting nitrogen in the second p-well while leaving the third photoresist film above each of the first p-well, first n-well and the second n-well, thereby forming a fifth nitridation region containing nitrogen in the third nitridation region as a portion thereof and having a fifth nitrogen concentration higher than the fourth nitrogen concentration to the boundary between the second p-well and the second gate insulative film, and
• (i) forming source and drain comprising the n-semiconductor region to each of the first p-well and the second p-well, after the step (h) and forming source and drain comprising a p-semiconductor region to each of the first n-well and the second n-well, after the step (h) above, thereby
• forming a first p-channel MISFET having source and drain comprising the p-semiconductor region, the first gate insulative film, a gate electrode containing the p-semiconductor piece and the second nitridation region in the first n-well,
• forming a second p-channel MISFET having source and drain comprising the p-semiconductor region, the second gate insulative film, a gate electrode containing the p-semiconductor piece and the first nitridation region in the second n-well,
• forming a first n-channel MISFET having source and drain comprising the n-semiconductor region, the first gate insulative film, a gate electrode containing the n-semiconductor piece and a fourth nitridation region in the first p-well, and
• forming a second n-channel MISFET having source and drain comprising the n-semiconductor region, the second gate insulative film, a gate electrode containing the n-semiconductor piece and a fifth nitridation region in the second p-well.

A method of manufacturing a semiconductor integrated circuit device comprising the following steps of:

• (a) forming a first p-well, a second p-well, a first n-well and a second n-well to a main surface of a semiconductor substrate, then forming a first gate insulative film to the surface for each of the first p-well and the first n-well, and forming a second gate insulative film having a thickness larger than that of the first gate insulative film to the surface for each of the second p-well and the second n-well,
• (b) applying a heat treatment to the semiconductor substrate in an atmosphere containing nitrogen, thereby forming a first nitridation region having a first nitrogen concentration to the boundary between the second p-well and the second gate insulative film and to the boundary between the second n-well and the second gate insulative film, and forming a second nitridation region having a second nitrogen concentration higher than the first nitrogen concentration to the boundary between the first p-well and the first gate insulative film and to the boundary between the first n-well and the first gate insulative film,
• (c) forming an n-silicon film above each of the first p-well and the second p-well, and forming a p-silicon film above each of the first n-well and the second n-well,
• (d) patterning each of the n-silicon film and the p-silicon film, thereby forming an n-semiconductor piece comprising the n-silicon film above each of the first p-well and the second p-well, and forming a p-semiconductor piece comprising the p-silicon film above each of the first n-well and the second n-well,
• (e) forming a first photoresist film above each of the first p-well, the first n-well and the second n-well after the step
• (d) above, and ion implanting n-impurities in the second p-well, thereby constituting a portion of source and drain,
• (f) ion implanting nitrogen in the second p-well while leaving the first photoresist film above each of the first p-well, the first n-well and the second n-well respectively, thereby forming a third nitridation region containing nitrogen in the first nitridation region as a portion thereof and having a third nitrogen concentration higher than the second nitrogen concentration to the boundary between the second p-well and the second gate insulative film,
• (g) forming a second photoresist film above each of the second p-well, the first n-well, the second n-well, and ion implanting n-impurities in the first p-well thereby constituting a portion of source and drain,
• (h) ion implanting nitrogen in the first p-well while leaving the second photoresist film above each of the second p-well, the first n-well and the second n-well, thereby forming a fourth nitridation region containing nitrogen in the second nitridation region as a portion thereof and having a fourth nitrogen concentration higher than the second nitrogen concentration and equal with or lower than the third nitridation concentration,
• (i) forming source and drain comprising an n-semiconductor region to each of the first p-well and the second p-well and forming source and drain comprising a p-semiconductor region to each of the first n-well and the second n-well after the step (h), thereby
• forming a first p-channel MISFET having source and drain comprising the p-semiconductor region, the first gate insulative film, a gate electrode containing the p-semiconductor piece and a second nitridation region in the first n-well,
• forming a second p-channel MISFET having source and drain comprising the p-semiconductor region, the second gate insulative film, a gate electrode including the p-semiconductor piece and the first nitridation region in the second n-well,
• forming a first n-channel MISFET having source and drain comprising the n-semiconductor region, the first gate insulative film, a gate electrode including the n-semiconductor piece and the fourth nitridation region in the first p-well, and
• forming a second n-channel MISFET having source and drain comprising the n-semiconductor region, the second gate insulative film, a gate electrode including the n-semiconductor piece and the third nitridation region in the second p-well.

A method of manufacturing a semiconductor integrated circuit device comprising the following steps of:

• (a) forming a first gate insulative film to a first region and a second region on a main surface of a semiconductor substrate and forming a second gate insulative film having a thickness larger than the first gate insulative film to a third region and a fourth region on the main surface of the semiconductor substrate,
• (b) applying a heat treatment to the semiconductor substrate in an atmosphere containing nitrogen, thereby forming a first nitridation region having a first nitrogen concentration to the boundary between the semiconductor substrate and the second gate insulative film in the third region and to the boundary between the semiconductor substrate and the second gate insulative film in the fourth region, and forming a second nitridation region having a second nitrogen concentration higher than the first nitrogen concentration to the boundary between the semiconductor substrate and the first gate insulative film in the first region and to the boundary between the semiconductor substrate and the first gate insulative film in the second region,
• (c) depositing a silicon film on the semiconductor substrate, then forming a first photoresist film on the silicon film in the second region and the fourth region and forming an n-silicon film by ion implanting n-impurities to the silicon film in the first region and the third region,
• (d) ion implanting p-impurities through the n-silicon film to the semiconductor substrate while leaving the first photoresist film on the silicon film in the second region and the fourth region, thereby forming a first p-well in the first region and forming a second p-well in the third region of the semiconductor substrate,
• (e) ion implanting nitrogen through the n-silicon film to each of the first p-well and the second p-well while leaving the first photoresist film on the silicon film in the second region and the fourth region, thereby
• forming a third nitridation region containing nitrogen in the first nitridation region as a portion thereof to the boundary between the second p-well and the second gate insulative film and
• forming a fourth nitridation region containing nitrogen in the second nitridation region as a portion thereof and having a fourth nitrogen concentration higher than the second nitrogen concentration to the boundary between the first p-well and the first gate insulative film,
• (f) forming a second photoresist film above each of the silicon film in the second region and the fourth region and the n-silicon film in the first region, and ion implanting n-impurities through the n-silicon film in the second p-well, thereby optimizing the threshold voltage of an n-channel MISFET formed in the second p-well,
• (g) ion implanting nitrogen through the n-silicon film in the second p-well while leaving the second photoresist film above each of the silicon film in the second region and the fourth region and the n-silicon film in the first region, thereby forming a fifth nitridation region containing nitrogen in the third nitridation region as a portion thereof and having a fifth nitrogen concentration equal with or higher than the fourth nitrogen concentration to the boundary between the second p-well and the second gate insulative film,
• (h) forming a third photoresist film on the n-silicon film and ion implanting p-impurities to the silicon film in the second region and the fourth region, thereby forming a p-silicon film,
• (i) ion implanting n-impurities through the p-silicon film into the semiconductor substrate while leaving the third photoresist film on the n-silicon film, thereby forming a first n-well in the second region and forming a second n-well in the fourth region of the semiconductor substrate,
• (j) patterning the n-silicon film and the p-silicon film, respectively, thereby forming an n-semiconductor piece comprising the n-silicon film above each of the first p-well and the second p-well, and forming a p-semiconductor piece comprising the p-silicon film above each of the first n-well and the second n-well, and
• (k) forming source and drain comprising an n-semiconductor region to the first p-well and the second p-well, respectively, and forming source and drain comprising a p-semiconductor region to the first n-well and the second n-well, respectively, after the step (j) thereby
• forming a first p-channel MISFET having source and drain comprising the p-semiconductor region, the first gate insulative film, a gate electrode including the p-semiconductor piece and the second nitridation region in the first n-well,
• forming a second p-channel MISFET having source and drain comprising the p-semiconductor region, the second insulative film, a gate electrode including the p-semiconductor piece and the first nitridation region in the second n-well,
• forming a first n-channel MISFET having source and drain comprising the n-semiconductor region, the first insulative film, a gate electrode including the n-semiconductor piece and the fourth nitridation region in the first p-well, and
• forming a second n-channel MISFET having source and drain comprising the n-semiconductor region, the second insulative film, a gate electrode containing the n-semiconductor piece and the fifth nitridation region in the second n-well,.

A method of manufacturing a semiconductor integrated circuit device comprising the following steps of;

• (a) forming a first agate insulative film in a first region on a main surface of a semiconductor substrate and forming a second gate insulative film having a thickness larger than the first gate insulative film in the second region on the main surface of the semiconductor substrate,
• (b) applying a heat treatment to the semiconductor substrate in an atmosphere containing nitrogen, thereby forming a first nitridation region having a first nitrogen concentration to the boundary between the semiconductor substrate and the second insulative film in the second region, and forming a second nitridation region having a second nitrogen concentration higher than the first nitrogen concentration to the boundary between the semiconductor substrate and the first gate insulative film in the first region,
• (c) forming a conductor film above the first and the second gate insulative films after the step (b), and ion implanting n-impurities through the conductor film to the semiconductor substrate in the first and the second regions for controlling the threshold voltage of a n-channel MISFET,
• (d) forming a photoresist film on the conductor film in the first region and ion implanting n-impurities through the conductor film in the second region to the semiconductor substrate in the second region, thereby optimizing the threshold voltage of the n-channel MISFET formed to the semiconductor substrate in the second region,
• (e) ion implanting nitrogen through the conductor film in the second region to the semiconductor substrate in the second region while leaving the photoresist film on the conductor film in the first region, thereby forming a third nitridation region containing nitrogen in the first nitridation region as a portion thereof and having a third nitrogen concentration equal with or higher than the second nitrogen concentration to the boundary between the semiconductor substrate in the second region and the second gate insulative film,
• (f) forming a semiconductor piece above each of the first and the second gate insulative films by patterning the conductor film,
• (g) forming source and drain comprising an n-semiconductor region to the semiconductor substrate in the first and the second regions, respectively, after the step (f) thereby forming a first n-channel MISFET having source and drain comprising the n-semiconductor region, the first gate insulative film, a gate electrode including the semiconductor piece and the second nitridation region to the semiconductor substrate in the first region and,
• forming a second n-channel MISFET having source and drain comprising the n-semiconductor region, the second gate insulative film a gate electrode including the semiconductor piece and the third nitridation region to the semiconductor substrate in the second region.

A method of manufacturing a semiconductor integrated circuit device comprising the following steps of:

• (a) forming p-well and n-well on a main surface of a semiconductor substrate and then forming a gate insulative film to the surface for each of the p-well and the n-well,
• (b) applying a heat treatment to the semiconductor substrate in an atmosphere containing nitrogen thereby forming a first nitridation region having a first nitrogen concentration to the boundary between the p-well and the gate insulative film and to the boundary between the n-well and the gate insulative film
• (c) forming a silicon film on the gate insulative film after the step (b),
• (d) covering the silicon film above the n-well with a first photoresist film, and ion implanting n-impurities in the silicon film above the p-well, thereby forming an n-silicon film,
• (e) ion implanting nitrogen through the n-silicon film to the p-well while leaving the first photoresist film on the silicon film, thereby forming a second nitridation region containing nitrogen in the first nitridation region as a portion thereof and having a second nitrogen concentration higher than the first nitrogen concentration to the boundary between the p-well and the gate insulative film,
• (f) covering the n-silicon film with a second photoresist film and ion implanting p-impurities in the silicon film above the n-well thereby forming a p-silicon film,
• (g) patterning each of the n-silicon film and the p-silicon film, thereby forming an n-semiconductor piece comprising the n-silicon film above the p-well and forming a p-semiconductor piece comprising the p-silicon film above the n-well, and
• (h) forming source and drain comprising an n-semiconductor region in the p-well and forming source and drain comprising a p-semiconductor region in the n-well after the step (g) thereby
• forming a p-channel MISFET having source and drain comprising the p-semiconductor region, the gate insulative film, a gate electrode including the p-semiconductor piece and the first nitridation film, in the n-well, and
• forming an n-channel MISFET having source and drain comprising the n-semiconductor region, the gate insulative film, a gate electrode including the n-semiconductor piece and the second nitridation region, in the p-well.