Device and method of low voltage SCR protection for high voltage failsafe ESD applications

A semiconductor circuit for multi-voltage operation having built-in ESD protection comprising:

• a drain extended MOS transistor located in a tank region of a first conductivity type, said drain extended MOS transistor including:
• a first portion of a well region of a second conductivity type opposite said first conductivity type located in said tank;
• a drain region of said second conductivity type located in said well region;
• a source region of said second conductivity type located in said tank and separated from said well region by a channel region in said tank;
• a gate extending over said channel region, said gate having an electrical connection to said source and ground potential;
• and
• a silicon controlled rectifier merged with said drain extended MOS transistor into said tank region, said silicon controlled rectifier including:
• a second portion of said well region of said second conductivity type;
• an anode region of the first conductivity type located in said well region, said anode region spaced from, but electrically connected to said drain region;
• a cathode region of the second conductivity type located in said tank, said cathode connected to electrical ground potential;
• a diffusion region of the second conductivity type positioned between said anode and said cathode such that one portion of said diffusion region is located in said tank and the other portion in said well, whereby said diffusion region is resistively coupled by said well to said drain of said MOS transistor;
• insulator layers located over each semiconductor spacing region between said anode, diffusion region, and cathode, said insulator layers having thicknesses suitable for high voltage operation.

A method of fabricating into the surface of a n-well, having first and second side-walls in a p-tank, a pnpn SCR integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, said surface having a layer of insulating material suitable as gate dielectric and a poly-silicon gate deposited on said insulating layer at the location where said first side-wall intersects said surface, comprising the steps of:

• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said p-tank area adjacent said poly-silicon gate and covering said n-well and said p-tank adjacent said second side-wall;
• implanting, at low energy and low dose, n-doping ions into said exposed surface area, thereby creating shallow, lightly n-doped layers under said surface and leaving the area under the photoresist unimplanted;
• removing said first photoresist layer;
• depositing a conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a second patterned photoresist layer to protect portions of said dielectric layer defining the bases of the pnp and the npn portions of said SCR;
• directional plasma etching said dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• removing said second photoresist layer;
• forming a third patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, n-doping ions into said surface, thereby creating n-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and as npn portion of said SCR, the junction of one of said SCR n-regions partially formed with said p-tank and partially with said n-well;
• removing said third photoresist layer;
• depositing a fourth photoresist layer and opening a window therein, thereby exposing the surface of said anode of said pnp portion of said SCR;
• implanting, at medium energy and high dose, p-doping ions into said window, thereby creating a p-doped region at medium depth, suitable as anode of said SCR;
• and
• removing said fourth photoresist layer.

A method of fabricating into the surface of a p-type semiconductor a pnpn silicon controlled rectifier (SCR) integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, comprising the steps of:

• forming non-conductive isolation regions into said p-type semiconductor for defining the lateral boundaries of the active areas of said MOS transistor and said SCR;
• implanting n-doping ions into said p-type semiconductor to form an n-well having side walls;
• implanting p-doping ions into said p-type semiconductor surrounding said n-well side walls to form a p-tank;
• depositing over said surface a layer of insulating material suitable as gate dielectric, thereby covering said SCR and transistor areas;
• depositing a layer of poly-silicon or other conductive material onto said insulating layer;
• protecting a portion of said poly-silicon and etching the remainder thereof, thereby defining the gate area of said transistor at the location where said n-well side wall intersects said surface;
• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said p-tank area adjacent said poly-silicon gate;
• implanting, at low energy, low dose n-doping ions into said exposed surface area, thereby creating shallow, lightly n-doped layers under said surface;
• removing said first photoresist layer;
• depositing a conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a second patterned photoresist layer to protect portions of said dielectric layer defining the bases of the pnp and the npn portions of said SCR;
• directional plasma etching said dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• removing said second photoresist layer;
• forming a third patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, n-doping ions into said surface, thereby creating n-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and as npn portions of said SCR;
• removing said third photoresist layer;
• depositing a fourth photoresist layer and opening a window therein, thereby exposing the surface of said anode of said pnp portion of said SCR;
• implanting, at medium energy and high dose, p-doping ions into said window, thereby creating a p-doped region at medium depth, suitable as anode of said SCR;
• removing said fourth photoresist layer;
• and
• removing said exposed gate dielectric and siliciding the freshly etched surfaces, thereby forming silicides only on the medium doped silicon regions.

A method of fabricating into the surface of a p-well, having first and second side-walls in a n-tank, a npnp SCR integrated with a drain-extended pMOS transistor for multi-voltage operation having built-in ESD protection, said surface having a layer of insulating material suitable as gate dielectric and a poly-silicon gate deposited on said insulating layer at the location where said first side wall intersects said surface, comprising the steps of:

• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said n-tank area adjacent said poly-silicon gate and covering said p-well and said n-tank adjacent said second side-wall;
• implanting, at low energy and low dose, p-doping ions into said exposed surface area, thereby creating shallow, lightly p-doped layers under said surface and leaving the area under the photoresist unimplanted;
• removing said first photoresist layer;
• depositing a conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a second patterned photoresist layer to protect portions of said dielectric layer defining the bases of the npn and pnp portions of said SCR;
• directional plasma etching said dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• removing said second photoresist layer;
• forming a third patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, p-doping ions into said surface, thereby creating p-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and as pnp portion of said SCR, the junction of one of said SCR p-regions partially formed with said n-tank and partially with said p-well;
• removing said third photoresist layer;
• depositing a fourth photoresist layer and opening a window therein, thereby exposing the surface of said anode of said npn portion of said SCR;
• implanting, at medium energy and high dose, n-doping ions into said window, thereby-creating a n-doped region at medium depth, suitable as anode of said SCR;
• and
• removing said fourth photoresist layer.

A method of fabricating into the surface of a n-type semiconductor a npnp SCR integrated with a drain-extended pMOS transistor for multi-voltage operation having built-in ESD protection, comprising the steps of:

• forming non-conductive isolation regions into said n-type semiconductor for defining the lateral boundaries of the active areas of said MOS transistor and said SCR;
• implanting p-doping ions into said n-type semiconductor to form an p-well having side walls;
• implanting n-doping ions into said n-type semiconductor surrounding said p-well side walls to form a n-tank;
• depositing over said surface a layer of insulating material suitable as gate dielectric, thereby covering said SCR and transistor areas;
• depositing a layer of poly-silicon or other conductive material onto said insulating layer;
• protecting a portion of said poly-silicon and etching the remainder thereof, thereby defining the gate area of said transistor at the location where said p-well side wall intersects said surface;
• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said n-tank area adjacent said poly-silicon gate;
• implanting, at low energy, low dose p-doping ions into said exposed surface area, thereby creating shallow, lightly p-doped layers under said surface;
• removing said first photoresist layer;
• depositing a conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a second patterned photoresist layer to protect portions of said dielectric layer defining the bases of the npn and pnp portions of said SCR;
• directional plasma etching said insulating layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• removing said second photoresist layer;
• forming a third patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, p-doping ions into said surface, thereby creating p-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and as pnp portions of said SCR;
• removing said third photoresist layer;
• depositing a fourth photoresist layer and opening a window therein, thereby exposing the surface of said cathode of said npn portion of said SCR;
• implanting, at medium energy and high dose, n-doping ions into said window, thereby creating a n-doped region at medium depth, suitable as cathode of said SCR;
• removing said fourth photoresist layer;
• and
• removing said exposed gate dielectric;
• and
• siliciding the freshly etched surfaces, thereby forming silicides only on the medium doped silicon regions.

A method of fabricating into the surface of a n-well, having first and second side-walls in a p-tank, a pnpn SCR integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, said surface having a layer of insulating material suitable as gate dielectric and a poly-silicon gate deposited on said insulating layer at the location where said first side-wall intersects said surface, comprising the steps of:

• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said p-tank area adjacent said poly-silicon gate and covering said n-well and said p-tank adjacent said second side-wall;
• implanting, at low energy and low dose, n-doping ions into said exposed surface area, thereby creating shallow, lightly n-doped layers under said surface and leaving the area under the photoresist unimplanted;
• removing said first photoresist layer;
• depositing a first conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• directional plasma etching said first dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• forming a second patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, n-doping ions into said surface, thereby creating n-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and said npn portions of said SCR;
• removing said second photoresist layer;
• depositing a third photoresist layer and opening a window therein, thereby exposing the surface of said anode of said pap portion of said SCR;
• implanting, at medium energy and high dose, p-doping ions into said window, thereby creating a p-doped region at medium depth, suitable as anode of said SCR;
• removing said third photoresist layer;
• depositing a second conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a fourth patterned photoresist layer to protect a portion of said conformal layer defining said SCR except for fractional surface portions of said anode and cathode;
• removing said second dielectric layer except for said photoresist-protected portion;
• removing said fourth photoresist layer;
• and
• siliciding the freshly etched surfaces, including said fractional anode and cathode surface portions, thereby leaving the dielectric-protected surface areas of said SCR silicide-blocked.

A method of fabricating into the surface of a p-type semiconductor a pnpn SCR integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, comprising the steps of:

• forming non-conductive isolation regions into said p-type semiconductor for defining the lateral boundaries of the active areas of said MOS transistor and said SCR;
• implanting n-doping ions into said p-type semiconductor to form a n-well having side walls;
• implanting p-doping ions into said p-type semiconductor surrounding said n-well side walls to form a p-tank;
• depositing over said surface a layer of insulating material suitable as gate dielectric, thereby covering said SCR and transistor areas;
• depositing a layer of poly-silicon or other conductive material onto said insulating layer;
• protecting a portion of said poly-silicon and etching the remainder thereof, thereby defining the gate area of said transistor at the location where said n-well side wall intersects said surface;
• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said p-tank area adjacent said poly-silicon gate;
• implanting, at low energy, low dose n-doping ions into said exposed surface area, thereby creating shallow, lightly n-doped layers under said surface;
• removing said first photoresist layer;
• depositing a first conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• directional plasma etching said first dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• forming a second patterned photoresist layer to protect a portion of said surface, defining the anode of said SCR;
• implanting, at medium energy, n-doping ions into said surface, thereby creating n-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and said npn portion of said SCR;
• removing said second photoresist layer;
• depositing a third photoresist layer and opening a window therein, thereby exposing the surface of said anode of said pnp portion of said SCR;
• implanting, at medium energy and high dose, p-doping ions into said window, thereby creating a p-doped region at medium depth, suitable as anode of said SCR;
• removing said third photoresist layer;
• depositing a second conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a fourth patterned photoresist layer to protect a portion of said second dielectric layer defining said SCR except for fractional surface portions of said anode and cathode;
• removing said second dielectric layer except for said photoresist-protected portion;
• removing said fourth photoresist layer;
• and
• siliciding the freshly etched surfaces, including said fractional anode and cathode surface portions, thereby leaving the dielectric-protected surface areas of said SCR silicide-blocked.

A method of fabricating into the surface of a p-well, having first and second side-walls in a n-tank, a npnp SCR integrated with a drain-extended pMOS transistor for multi-voltage operation having built-in ESD protection, said surface having a layer of insulating material suitable as gate dielectric and a poly-silicon gate deposited on said insulating layer at the location where said first side-wall intersects said surface, comprising the steps of:

• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said n-tank area adjacent said poly-silicon gate and covering said p-well and said n-tank adjacent said second side-wall;
• implanting, at low energy and low dose, p-doping ions into said exposed surface area, thereby creating shallow, lightly p-doped layers under said surface and leaving the area under the photoresist unimplanted;
• removing said first photoresist layer;
• depositing a first conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• directional plasma etching said first dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• forming a second patterned photoresist layer to protect a portion of said surface defining the anode of said SCR;
• implanting, at medium energy, p-doping ions into said surface, thereby creating p-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and said pnp portions of said SCR;
• removing said second photoresist layer;
• depositing a third photoresist layer and opening a window therein, thereby exposing the surface of said anode of said npn portion of said SCR;
• implanting, at medium energy and high dose, n-doping ions into said window, thereby creating a n-doped region at medium depth, suitable as anode of said SCR;
• removing said third photoresist layer;
• depositing a second conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a fourth patterned photoresist layer to protect a portion of said conformal layer defining said SCR except for fractional surface portions of said anode and cathode;
• removing said second dielectric layer except for said photoresist-protected portion;
• removing said fourth photoresist layer;
• and
• siliciding the freshly etched surfaces, including said fractional anode and cathode surface portions, thereby leaving the dielectric-protected surface areas of said SCR silicide-blocked.

A method of fabricating into the surface of a n-type semiconductor a npnp SCR integrated with a drain-extended nMOS transistor for multi-voltage operation having built-in ESD protection, comprising the steps of:

• forming non-conductive isolation regions into said n-type semiconductor for defining the lateral boundaries of the active areas of said MOS transistor and said SCR;
• implanting p-doping ions into said n-type semiconductor to form a p-well having side walls;
• implanting n-doping ions into said n-type semiconductor surrounding said p-well side walls to form a n-tank;
• depositing over said surface a layer of insulating material suitable as gate dielectric, thereby covering said SCR and transistor areas;
• depositing a layer of poly-silicon or other conductive material onto said insulating layer;
• protecting a portion of said poly-silicon and etching the remainder thereof, thereby defining the gate area of said transistor at the location where said p-well side wall intersects said surface;
• depositing a first photoresist layer and opening a window therein, thereby exposing the surface of said n-tank area adjacent said poly-silicon gate;
• implanting, at low energy, low dose p-doping ions into said exposed surface area, thereby creating shallow, lightly p-doped layers under said surface;
• removing said first photoresist layer;
• depositing a first conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• directional plasma etching said first dielectric layer so that the only remaining dielectric forms side walls around said poly-silicon gate and covers the extent of the base space charge regions of said transistor;
• forming a second patterned photoresist layer to protect a portion of said surface, defining the anode of said SCR;
• implanting, at medium energy, p-doping ions into said surface, thereby creating p-doped regions that extend to a medium depth under said surface, suitable as deep source and drain of said transistor and said pnp portion of said SCR;
• removing said second photoresist layer;
• depositing a third photoresist layer and opening a window therein, thereby exposing the surface of said anode of said npn portion of said SCR;
• implanting, at medium energy and high dose, n-doping ions into said window, thereby creating a n-doped region at medium depth, suitable as anode of said SCR;
• removing said third photoresist layer;
• depositing a second conformal layer of dielectric material including silicon nitride or silicon dioxide over said surface;
• forming a fourth patterned photoresist layer to protect a portion of said second dielectric layer defining said SCR except for fractional surface portions of said anode and cathode;
• removing said second dielectric layer except for said photoresist-protected portion;
• removing said fourth photoresist layer;
• and
• siliciding the freshly etched surfaces, including said fractional anode and cathode surface portions, thereby leaving the dielectric-protected surface areas of said SCR silicide-blocked.