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AssigneeInternational Business Machines Corporation
InventorsJohn Walter Golz, Babar Khan, Joyce C. Liu, Christopher Joseph Waskiewicz, Teresa Jacqueline Wu
Estimating the term…
As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.
A method of simultaneously patterning features having a first width in a first portion of an integrated circuit, and having a second width in a second portion of an integrated circuit, comprising:
A front-end-of-line (FEOL) processing method of simultaneously patterning polysilicon features having a first linewidth in a first portion of an integrated circuit, and having a second linewidth in a second portion of an integrated circuit, comprising:
Dependencies are inferred from the claim text.