Method for forming MRAM bit having a bottom sense layer utilizing electroless plating

A method of fabricating a memory cell, said method comprising the steps of:

• forming a conductive layer in a trench of an insulating layer;
• forming a dielectric layer over said conductive layer and said insulating layer;
• forming a opening in said dielectric layer over said conductive layer;
• forming a sense layer in said opening;
• planarizing an upper surface of said sense layer and said dielectric layer;
• forming a tunnel barrier layer over said sense layer and said dielectric layer;
• forming a pinned layer over said tunnel barrier layer;
• and
• patterning said pinned layer, said tunnel barrier layer and said dielectric layer to form a memory cell.

A method of fabricating a memory cell, said method comprising the steps of:

• forming a conductive layer in a trench of an insulating layer;
• forming a dielectric layer over said conductive layer and said insulating layer;
• forming an opening in said dielectric layer over said conductive layer;
• electroplating a sense layer in said opening;
• planarizing an upper surface of said sense layer and said dielectric layer;
• forming a nonmagnetic tunnel barrier layer over said sense layer and said dielectric layer;
• forming a pinned layer over said nonmagnetic tunnel barrier layer;
• and
• patterning said pinned layer, nonmagnetic tunnel barrier layer and said dielectric layer to form a memory cell.

A magnetic random access memory structure comprising:

• a longitudinally extending planarized conductive line formed within an insulating layer;
• an electroplated bottom sense layer over said conductive line;
• a nonmagnetic tunnel barrier layer over said sense layer;
• a pinned layer over said nonmagnetic layer;
• and
• at least one electrical conductor in contact with said pinned layer.