US 2003/0215972 A1Published application

Single wafer fabrication of integrated micro-fluidic system

AssigneesInstitute of Microelectronics, National University of Singapore

InventorsQuanbo Zou, Yu Chen, Janak Singh, Tit Meng Lim, Tie Yan, Chew Kiat Heng

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Abstract

Formation of micro-fluidic systems is normally achieved using a multi-wafer fabrication procedure. The present invention teaches how a complete micro-fluidic system can be implemented on a single chip. The invention uses only dry etch processes to form micro-chambers. In particular, it makes use of deep reactive ion etching whereby multiple trenches of differing depths may be formed simultaneously. Buried micro-chambers are formed by isotropically increasing trench widths using an etchant that does not attack the mask so the trenches grow wider beneath the surface until they merge. Deposition of a dielectric layer over the trenches allows some trenches to be sealed and some to be left open. Micro-pumps are formed by including in the micro-chamber roof a layer that is used to change chamber volume either through electrostatically induced motion or through thermal mismatch as a result of its being heated.

Claims31

Dependent claims

A process to manufacture an integrated micro-fluidic system, comprising:

limiting all etching steps, with the exception of silicon backside etching, to dry etch processes;
providing a silicon body having a topmost surface beneath which are one or more integrated circuits;
on said topmost surface, depositing a first dielectric layer;
on said first dielectric layer, depositing a conductive layer and forming therefrom a pattern that includes at least one contact pad connected to said integrated circuits;
on said conductive and first dielectric layer, depositing a second dielectric layer;
patterning said second dielectric layer to form therein a plurality of openings such that at least two of said openings have different widths from each other, said openings extending downward as far as said topmost surface;
then, using said second dielectric layer as a hard mask, performing deep reactive ion etching whereby trenches are etched into said silicon body at said openings, said trenches etching at rates that are proportional to their widths, with trenches having wider openings being etched at faster rates;
with said second dielectric layer remaining in place, performing isotropic etching of said silicon body whereby said trenches grow wider while said openings remain unchanged;
continuing said isotropic etching until at least two trenches merge to form a single cavity;
then depositing a third dielectric layer to a thickness sufficient to seal all trenches whose openings have a width that is less than two times said thickness;
and
selectively removing said second and third dielectric layers so as to expose said contact pads.

9 more elements

A process to manufacture an integrated micro-fluidic system, including a micro-pump, comprising:

limiting all etching steps, with the exception of silicon backside etching, to dry etch processes;
providing a silicon body having a topmost surface beneath which are one or more integrated circuits;
on said topmost surface, depositing a first dielectric layer;
on said first dielectric layer, depositing a conductive layer and forming therefrom an electrode, that is electrically insulated from said silicon wafer, as well as at least one contact pad connected to said integrated circuits;
on said conductive and first dielectric layer, depositing a second dielectric layer;
patterning said second dielectric layer to form therein a plurality of openings such that at least two of said openings have different widths from each other, said openings extending downward as far as said topmost surface;
then, using said second dielectric layer as a hard mask, performing deep reactive ion etching whereby trenches are etched into said silicon body at said openings, said trenches having depths that are proportional to their widths, with wider openings leading to deeper trenches;
with said second dielectric layer remaining in place, performing isotropic etching of said silicon body whereby said trenches grow wider while said openings remain unchanged;
continuing said isotropic etching until at least two trenches merge to form a cavity, having a volume, below said electrode;
then depositing a third dielectric layer to a thickness sufficient to seal all trenches whose openings have a width that is less than two times said thickness, whereby said cavity becomes covered by a membrane comprising said electrode, said first dielectric layer, said second dielectric layer, and said third dielectric layer;
providing electrical connections to said electrode and said silicon body whereby, through application of voltage, electrostatic interaction between said electrode and said silicon body will occur causing said membrane to bow, thereby changing the volume of said cavity and causing a pumping action on any fluid within said cavity;
and
selectively removing said second and third dielectric layers so as to expose said contact pads.

10 more elements

A process to manufacture an integrated micro-fluidic system, including a micro-pump, comprising:

limiting all etching steps to dry etch processes and depositing at least two layers that have different coefficients of thermal expansion;
providing a silicon body having a topmost surface beneath which are one or more integrated circuits;
on said topmost surface, depositing a first dielectric layer;
on said first dielectric layer, depositing a conductive layer and forming therefrom a resistive element, that is electrically insulated from said silicon wafer, as well as at least one contact pad connected to said integrated circuits;
on said conductive and first dielectric layer, depositing a second dielectric layer;
patterning said second dielectric layer to form therein a plurality of openings such that at least two of said openings have different widths from each other, said openings extending downward as far as said topmost surface;
then, using said second dielectric layer as a hard mask, performing deep reactive ion etching whereby trenches are etched into said silicon body at said openings, said trenches having depths that are proportional to their widths, with wider openings leading to deeper trenches;
with said second dielectric layer remaining in place, performing isotropic etching of said silicon body whereby said trenches grow wider while said openings remain unchanged;
continuing said isotropic etching until at least two trenches merge to form a cavity, having a volume;
then depositing a third dielectric layer to a thickness sufficient to seal all trenches whose openings have a width that is less than two times said thickness, whereby said cavity becomes covered by a membrane comprising said resistive element, said first dielectric layer and said second dielectric layer and said third dielectric layer;
providing electrical connections to said resistive element whereby, through application of voltage, said membrane is heated by said resistive element and bows, thereby changing the volume of said cavity and causing a pumping action;
and
selectively removing said second and third dielectric layers so as to expose said contact pads.

10 more elements

A process to manufacture an integrated micro-fluidic system, including a thermally isolated micro-chamber, comprising:

providing a silicon wafer having a topmost surface beneath which are one or more integrated circuits;
on said topmost surface, depositing a first dielectric layer;
on said first dielectric layer, depositing a conductive layer and forming therefrom a resistive element, that is electrically insulated from said silicon wafer, as well as at least one contact pad connected to said integrated circuits;
on said conductive and first dielectric layer, depositing a second dielectric layer;
patterning said second dielectric layer to form therein a plurality of openings such that at least two of said openings have different widths from each other, said openings extending downward as far as said topmost surface;
then, using said second dielectric layer as a hard mask, performing deep reactive ion etching whereby trenches are etched into said silicon wafer at said openings, said trenches having depths that are proportional to their widths, with wider openings leading to deeper trenches;
with said second dielectric layer remaining in place, performing isotropic etching of said silicon wafer whereby said trenches grow wider while said openings remain unchanged;
continuing said isotropic etching until at least two trenches merge to form a cavity, having a volume;
then depositing a third dielectric layer to a thickness sufficient to seal all trenches whose openings have a width that is less than two times said thickness, whereby said cavity becomes a micro-chamber covered by a membrane comprising said resistive element, said first dielectric layer, said second dielectric layer and said third dielectric layer, there being on opposing sides, and adjacent to, said micro-chamber unsealed trenches, having floors, whose depth exceeds that of said cavity;
selectively etching said silicon wafer from its underside over an area that includes said micro-chamber and said trenches adjacent thereto, to a depth sufficient to expose said third dielectric layer on the floors of said adjacent trenches, thereby thermally isolating said micro-chamber;
providing electrical connections to said resistive element whereby, through application of voltage said micro-chamber and it contents are heated by said resistive element;
and
selectively removing said second and third dielectric layers so as to expose said contact pads.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/147,006Filed 16 May 2002
Published: 20 Nov 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

B81C 1/00214
For manufacturing microsystems: processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
F04B 43/043
Pumps having electric drive: micropumps
B81C 2201/0132
Etching: dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
B81C
Processes or apparatus specially adapted for the manufacture or treatment of microstructural

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US 6,716,661 B2Related patent
US 2003/0215972 A1This patent

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