Stacked local interconnect structure and method of fabricating same
AssigneeMicron Technology, Inc.
InventorJigish D. Trivedi
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AssigneeMicron Technology, Inc.
InventorJigish D. Trivedi
Estimating the term…
A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.
A method for minimizing etching damage of a semiconductor substrate having a plurality of features, comprising:
A method for minimizing etching damage of a semiconductor device having a plurality of features on portions thereof comprising:
A method for minimizing etching damage of at least one semiconductor device on a wafer, said at least one semiconductor device having a plurality of features comprising:
Dependencies are inferred from the claim text.