Method for forming polysilicon connected deep trench dram cell

A method for forming polysilicon connected deep trench DRAM cell, said method comprising:

• providing a substrate, wherein said substrate sequentially has a pad oxide layer thereon, a first mask layer on said pad oxide layer, a second mask layer on said first mask layer, and a photoresist layer on said second mask layer;
• etching said second mask layer, said first mask layer, said pad oxide layer, and said substrate to form an opening under a photoresist opening, wherein a lower portion of the opening in said substrate is a deep trench;
• removing said photoresist layer and said second mask layer;
• driving in a buried plate in said substrate, wherein said buried plate surrounding a lower portion of said deep trench;
• forming a capacitor dielectric layer to fill into a lower portion of said deep trench;
• forming a dielectric collar layer on a sidewall of said deep trench about said capacitor dielectric layer, wherein said dielectric collar layer covers an exposed surface of said capacitor dielectric layer within said deep trench but not fully covers the sidewall of said deep trench;
• forming a selective growth polysilicon layer to fill into said deep trench of said opening;
• etching said selective growth polysilicon layer to stop on said pad oxide layer;
• forming a shallow trench isolation structure in sidewall of said deep trench;
• forming a metal-oxide-semiconductor transistor on said substrate;
• forming a spacer on sidewall of said metal-oxide semiconductor transistor;
• forming a polysilicon layer on said metal-oxide semiconductor transistor;
• and
• etching back said polysilicon layer.