Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
AssigneeHewlett-Packard Development Company, L.P.
InventorsJoseph W. Ku, Paul Vande Voorde
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Abstract
The apparatus and method for forming de-coupling capacitors on top of SOC VLSI chip. The introduced large amount of de-coupling capacitor is intended to solve the power delivery problem of highly integrated and powered VLSI chip, especially in the Silicon-On-Insulator (SOI) technology. This invention proposes a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost. This design scheme is especially effective when the VLSI technology is scaled down further.
Claims20
A method of forming an integrated circuit comprising the steps of:
- forming circuit function block on an IC chip;
- and
- forming a decoupling capacitor in an area above the circuit function block.
A method of forming an integrated circuit comprising the steps of:
- forming a circuit function block on an IC chip;
- forming a first metal layer separating a decoupling capacitor circuit from the circuit function block;
- and
- forming an inter-digitated capacitance structure on the first metal layer, wherein the inter-digitated capacitance structure is etched to form a predetermined pattern of inter-digitated metal fingers.
An integrated circuit comprising:
- a circuit function block having a predetermined circuit layout;
- and
- an inter-digitated capacitance structure comprising at least one metal plate and a plurality of inter-digitated metal fingers on top of the circuit function block.
Dependencies are inferred from the claim text.