Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material of a first conductivity type;
• first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween;
• a first insulation layer disposed over said substrate;
• an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of the channel region and- over a portion of the first region, wherein the floating gate includes a pair of opposing raised sharp edges;
• a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and
• an electrically conductive control gate having a first portion disposed adjacent to and insulated from the floating gate and a second portion extending over a portion of the second insulation layer and over a portion of the floating gate including a portion of both of the raised sharp edges.

An array of electrically programmable and erasable memory devices, comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including a plurality of memory cells extending in the first direction, each of the memory cells including:
• first and second spaced-apart regions formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween,
• a first insulation layer disposed over said substrate including over said channel region,
• an electrically conductive floating gate disposed over the first insulation layer and extending over a portion of the channel region and over a portion of the first region, wherein the floating gate includes a pair of opposing raised sharp edges,
• a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and
• an electrically conductive control gate having a first portion disposed adjacent to and insulated from the floating gate and a second portion extending over a portion of the second insulation layer and over a portion of the floating gate including a portion of the pair of raised sharp edges.