Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
AssigneeLSI Logic Corporation
InventorsDerryl Allman, John Gregory
Life of this patent
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AssigneeLSI Logic Corporation
InventorsDerryl Allman, John Gregory
Estimating the term…
Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
A vertical metal-insulator-metal (VMIM) capacitor in an integrated circuit (IC) that has a horizontal substrate, a lower metal interconnect layer and an upper damascene-metallization interconnect layer, the lower metal interconnect layer and the substrate being separated by a dielectric layer, the lower metal interconnect layer and the upper damascene-metallization interconnect layer being separated by an interlayer dielectric (ILD) layer, the upper damascene-metallization interconnect layer being at least partially formed by damascene-metallization steps, comprising:
In a vertical metal-insulator-metal (VMIM) capacitor formed at least partially in an interlayer dielectric (ILD) layer between horizontal first and second metal interconnect layers in an integrated circuit (IC), the first metal interconnect layer being separated from a substrate of the IC by at least one dielectric layer, the first and second metal interconnect layers being connected by a via extending substantially vertically through the ILD layer, the VMIM capacitor comprising first and second substantially vertical plates separated by capacitor dielectric material, and an improvement wherein:
Dependencies are inferred from the claim text.