Method for fabricating an integrated semiconductor circuit
AssigneeInfineon Technologies AG
InventorsHelge Altfeld, Monika Gschoderer, Michael Eisenhut, Marc Walter, Beate Frankowsky
Life of this patent
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Abstract
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on respectively different layer types. In this manner, the at least two different wiring forms can be individually and jointly analyzed.
Claims6
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the step of:
- drawing each of the different wiring forms as respectively different layer types.
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the step of:
- distinguishing the two different wiring forms as a short-range wiring form and a wide-range wiring form that can be automatically identified in a drawing as the respectively different layer types, the wide-range wiring form substantially containing wirings for signal and supply lines for a plurality of function blocks, and the short-range wiring form substantially containing wirings of individual components within a function block;
- drawing each of the different wiring forms as respectively different layer types by the steps of:
- drawing the wide-range wiring form using an automatic wiring tool;
- drawing the short-range wiring form based on a macro level and largely manually;
- and
- automatically manipulating structures stored as data during a chip design by carrying out a manipulation for the wide-range wiring form and the short-range wiring form with in each case specific values depending on the respectively defined layer types.
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the step of:
- distinguishing the two different wiring forms as a short-range wiring form and a wide-range wiring form that can be automatically identified in a drawing as the respectively different layer types, the wide-range wiring form substantially containing wirings for signal and supply lines for a plurality of function blocks, and the short-range wiring form substantially containing wirings of individual components within a function block;
- drawing each of the different wiring forms as respectively different layer types by the steps of:
- drawing the wide-range wiring form using an automatic wiring tool;
- drawing the short-range wiring form based on a macro level and largely manually;
- and
- automatically checking technological specifications for a physical chip design using software by checking structures stored as data for the short-range wiring form and for the wide-range wiring form with in each case specific values depending on the respectively defined layer types.
Dependencies are inferred from the claim text.