Method for forming a flash reference cell

Abstract

A method is used to form a flash reference memory cell and comprises the following steps. A floating well is formed in a substrate. A first dielectric layer is formed to cover the substrate. A defined floating gate is formed on the first dielectric layer and aligned with the floating well. A second dielectric layer is formed on the substrate. A contact window is formed by defining the second dielectric layer to expose portions of the floating gate. A heavy ion implantation is performed on the exposed floating gate. A third dielectric layer is formed to cover the substrate and fills the contact window. The well region in the substrate is used as the isolation between the floating gate and the substrate to prevent the problems of over-etching in the contact window process and misalignment in the floating gate process. The heavy ion implantation process increases the amount of the dopant in the floating gate to reduce the resistance of the floating gate window, to improve the RC delay of the flash reference memory cell, and further to enhance the operation speed of the device.

Dependencies are inferred from the claim text.