Semiconductor memory circuitry

An integrated circuit comprising:

• a semiconductor die;
• a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array formed on the semiconductor die;
• column addressing circuitry formed on the semiconductor die and coupled to the memory cells for addressing columns of the memory cells, and
• sense amplifier circuitry formed on the semiconductor die and coupled to the memory cells for sensing signals from rows of the memory cells;
• wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.

A plurality of integrated circuits comprising:

• a processed semiconductor wafer ready for dicing;
• and
• a plurality of die sites on the processed semiconductor wafer;
• wherein a predominant number of the total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable memory cells arranged in at least one array, circuitry coupled to the memory cells for permitting data to be written to and read from the memory cells, and at least one area of 100 square microns of continuous surface area of the processed semiconductor wafer having at least 170 of the memory cells.

A plurality of integrated circuits comprising:

• a processed semiconductor wafer ready for dicing;
• and
• a plurality of die sites on the processed semiconductor wafer;
• wherein a predominant number of the total number of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array, column addressing circuitry coupled to the memory cells for addressing columns of the memory cells, sense amplifier circuitry coupled to the memory cells for sensing signals from rows of the memory cells, and at least one area of 100 square microns of continuous surface area of the processed semiconductor wafer having at least 170 of the memory cells.