US 2003/0067031 A1 · Nonvolatile memory structures and fabrication methods

Abstract

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Claims19

Dependent claims

A semiconductor integrated circuit comprising a memory comprising:

one or more pairs of first structures positioned over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure;
wherein for each pair of first structures S1, S2, the memory comprises:
a plurality of doped regions in the semiconductor substrate, each doped region providing a source/drain region to a memory cell having floating and control gates in the structure S1 and also providing a source/drain region to a memory cell having floating and control gates in the structure S2;
and
a second conductive line formed over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S1 and S2 and physically contacts the doped regions which provide the source/drain regions to the memory cells having floating and control gates in the structures S1, S2.

2 more elements

A method for fabricating a semiconductor integrated circuit comprising a memory array, the method comprising:

forming a first insulating layer over a semiconductor substrate;
forming a first conductive layer over the first insulating layer;
forming a second insulating layer over the first conductive layer;
forming a second conductive layer over the second insulating layer;
patterning the first and second conductive layers and the second insulating layer to form a plurality of first structures each of which comprises:
a plurality of floating gates for a plurality of memory cells, the floating gates being formed from the first conductive layer;
and
conductive line made from the second conductive layer and providing control gates for the memory cells;
forming doped regions in the substrate which provide source/drain regions to memory cells of the memory array, such that each first structure has a first sidewall adjacent to a plurality of the doped regions;
forming a third conductive layer over the first structures;
anisotropically etching the third conductive layer, the etching operation being performed without masking the third conductive layer over the memory array, the etching operation forming, from the third conductive layer:
a spacer over a second sidewall of each first structure;
one or more conductive lines each of which extends between adjacent first sidewalls of two first structures and physically contacts the doped regions to which the adjacent first sidewalls are adjacent;
forming an insulator over the spacers and conductive lines made from the third conductive layer.

11 more elements

Dependencies are inferred from the claim text.

Nonvolatile memory structures and fabrication methods

Life of this patent

Nonvolatile memory structures and fabrication methods

Life of this patent

Abstract

Claims19