Barium strontium titanate annealing process
AssigneeApplied Materials, Inc.
InventorsAnnabel Susan Nickles, Ravi Rajagopalan, Pravin Narwankar
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Abstract
The present invention provides a means for obtaining dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500° C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.
Claims24
A process for forming a dielectric layer on a surface, comprising the steps of:
- a) depositing a layer of a high-K dielectric material over a surface, wherein the deposition occurs at a temperature of less than 500° C.;
- and
- b) annealing the dielectric layer to the surface using a high temperature post-deposition annealing process;
- wherein the process results in a dielectric layer characterized by substantially even coverage of the surface and a crystal structure characterized by having a high dielectric constant.
A MIM DRAM capacitor comprising:
- an first electrode comprising a metal selected from the group consisting of platinum. Rubidium, and iridium;
- a layer of a high-K dielectric material deposited on said electrode, wherein the deposition of the dielectric material occurs at a temperature of less than 500° C. and annealing of the dielectric material to the surface occurs using high temperature post-deposition annealing process, and
- a second electrode comprising a metal selected from the group consisting of platinum, rubidium, and iridium.
A capacitor within an integrated circuit, comprising:
- a layer of a high-K dielectric material over a surface, wherein the deposition of the dielectric material occurs at a temperature of less than 500° C. and annealing of the dielectric material to the surface occurs using a high temperature post-deposition annealing process.
A method of fabricating a MIM DRAM capacitor, comprising the steps of:
- depositing a first metal layer onto a substrate;
- depositing a high-K dielectric material over a surface, wherein the deposition of the dielectric material occurs at a temperature of less than 500° C. and annealing of the dielectric material to the surface occurs at a temperature of at least 650° C.;
- and
- depositing a second metal layer onto the dielectric material.
A semiconductor device comprising:
- a semiconductor substrate where a semiconductor integrated circuit is formed;
- a capacitor formed on an insulated surface of the semiconductor substrate, the capacitor comprising of a pair of electrodes and a dielectric layer between the electrodes, wherein the dielectric layer is comprised of a high-K dielectric material deposited at a temperature of less than 500° C. and annealing of the dielectric material to the surface occurs using a high temperature post-deposition annealing process;
- and
- an interconnection layer which operatively connects between one of the electrodes and the semiconductor integrated circuit.
A process for forming a dielectric layer on a surface, comprising the steps of:
- a) depositing a layer of BST over a surface, wherein the deposition occurs at a temperature of less than 500° C.;
- and
- b) annealing the BST layer to the surface using a post-deposition annealing process at a temperature greater than 500° C.;
- wherein the process results in a dielectric layer characterized by substantially even coverage of the surface and a crystal structure characterized by having a high dielectric constant.
A process for forming a dielectric layer on a surface, comprising the steps of:
- a) depositing a layer of a high-K dielectric material over a surface, wherein the deposition occurs at a temperature of less than 500° C.;
- and
- b) annealing the dielectric layer to the surface using remote plasma annealing at a temperature of about 500° C. to about 800° C.;
- a high temperature post-deposition annealing process;
- wherein the process results in a dielectric layer characterized by substantially even coverage of the surface and a crystal structure characterized by having a high dielectric constant.
Dependencies are inferred from the claim text.