Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory

An Flash memory cell device with a parasitic surface transfer transistor (PASTT) comprising:

• a semiconductor substrate comprising an active area and a shallow trench isolation;
• a source junction in said active area;
• a drain junction in said active area;
• a cell channel in said active area extending from said drain junction to said source junction;
• parasitic channels in said active area on the top surface of said semiconductor substrate extending from said drain junction to said source junction, bounded on one side by said isolation barrier region, and bounded on another other side by said cell channel;
• a floating gate comprising a first polysilicon layer overlying said cell channel with a tunneling oxide layer therebetween wherein said floating gate does not overlie said parasitic channels;
• a control gate comprising a second polysilicon layer overlying said floating gate with an interlevel dielectric layer therebetween;
• and
• a parasitic surface transfer transistor (PASTT) gate comprising said second polysilicon layer overlying said parasitic channels with said interlevel dielectric layer therebetween wherein said PASTT gate inverts said parasitic channels to turn ON said PASTT at a parasitic threshold voltage.

A method to form a Flash memory device with Flash memory cells and parasitic surface transfer transistor (PASTT) devices in the manufacture of an integrated circuit device comprising:

• depositing a tunneling oxide layer overlying a semiconductor substrate;
• depositing a first conductive layer overlying said tunneling oxide layer;
• patterning said first conductive layer and said tunneling oxide layer to define the cell width edges of floating gates for planned Flash memory cells and to expose said semiconductor substrate where shallow trench isolations are planned;
• forming temporary sidewall spacers on said cell width edges of said first conductive layer;
• thereafter etching said exposed semiconductor substrate to form trenches for said planned shallow trench isolations;
• depositing a trench filling oxide layer overlying said first conductive layer and said temporary sidewall spacers and filling said trenches;
• polishing down said trench filling oxide layer to complete said shallow trench isolations and to thereby define active areas in said semiconductor substrate;
• removing said temporary sidewall spacers to thereby expose said active areas between said shallow trench isolations and said cell width edges of said first conductive layer wherein said exposed active areas form parasitic channels and unexposed said active areas form cell channels;
• thereafter ion implanting said semiconductor substrate to thereby adjust the threshold voltages of said Flash memory cells and of said PASTT devices;
• thereafter depositing an interlevel dielectric layer overlying said first conductive layer and said parasitic channels;
• depositing a second conductive layer overlying said interlevel dielectric layer wherein parasitic transistor gates are formed where said second conductive layer overlies said parasitic channels with said interlevel dielectric layer therebetween;
• patterning said second conductive layer, said interlevel dielectric layer, said first conductive layer, and said tunneling oxide to thereby form control gates and to define the cell length edges of said floating gates for said Flash memory cells wherein floating gates are formed where said first conductive layer overlies said cell channels with said tunneling oxide layer therebetween and wherein control gates are formed where said second conductive layer overlies said floating gates with said interlevel dielectric layer therebetween;
• and
• thereafter implanting ions into said semiconductor substrate to form source and drain junctions to complete said Flash memory cells and said PASTT devices in the manufacture of the Flash memory device.

A method to form a Flash memory device with Flash memory cells and parasitic surface transfer transistors (PASTT) devices in the manufacture of an integrated circuit device comprising:

• depositing a tunneling oxide layer overlying a semiconductor substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer;
• patterning said first polysilicon layer and said tunneling oxide layer to define the cell width edges of floating gates for planned Flash memory cells and to expose said semiconductor substrate where shallow trench isolations are planned;
• forming temporary sidewall spacers on said cell width edges of said first polysilicon layer wherein said temporary sidewall spacers comprise silicon nitride;
• thereafter etching said exposed semiconductor substrate to form trenches for said planned shallow trench isolations;
• depositing a trench filling oxide layer overlying said first polysilicon layer and said temporary sidewall spacers and filling said trenches;
• polishing down said trench filling oxide layer to complete said shallow trench isolations and to thereby define active areas in said semiconductor substrate;
• removing said temporary sidewall spacers to thereby expose said active areas between said shallow trench isolations and said cell width edges of said first polysilicon layer wherein said exposed active areas form parasitic channels and unexposed said active areas form cell channels;
• thereafter ion implanting said semiconductor substrate to thereby adjust the threshold voltages of said Flash memory cells and of said PASTT devices;
• thereafter depositing an interlevel dielectric layer overlying said first polysilicon layer and said parasitic channels;
• depositing a second polysilicon layer overlying said interlevel dielectric layer wherein parasitic transistor gates are formed where said second polysilicon layer overlies said parasitic channels with said interlevel dielectric layer therebetween;
• patterning said second polysilicon layer, said interlevel dielectric layer, said first polysilicon layer, and said tunneling oxide to thereby form control gates and to define the cell length edges of said floating gates for said Flash memory cells wherein said floating gates are formed where said first polysilicon layer overlies said cell channels with said tunneling oxide layer therebetween and wherein said control gates are formed where said second polysilicon layer overlies said floating gates with said interlevel dielectric layer therebetween;
• thereafter implanting ions into said semiconductor substrate to form lightly doped regions;
• thereafter forming permanent sidewall spacers on said control gates and said floating gates;
• and
• thereafter implanting ions into said semiconductor substrate to form source and drain junctions to complete said Flash memory cells and said PASTT devices in the manufacture of the Flash memory device.