Guard mesh for noise isolation in highly integrated circuits

A method of designing an integrated circuit for manufacture at and on a semiconductor substrate die surface, said method comprising

• partitioning and placing circuitry of said integrated circuit according to noise characteristics of said circuitry from a netlist of said integrated circuit;
• further partitioning said circuitry into circuit blocks sharing power supplies, said circuit blocks having first and opposite conductivity type diffusion guard band meshes disposed therearound, and defining metal power supply meshes for said circuit blocks to substantially overlie said first conductivity type diffusion guard band meshes and said opposite conductivity type diffusion guard band meshes for intimate electrical contact with and along said first conductivity type and opposite conductivity type diffusion guard band meshes;
• testing said partitioned circuitry against predetermined criteria;
• and
• repeating said partitioning step and said further partitioning and defining step selectively responsive to failure of said partitioned circuitry against said predetermined criteria until said partitioned circuitry passes said predetermined criteria.