Method for forming a silicide gate stack for use in a self-aligned contact etch
OwnerMax F. Hinemaninventor
Life of this patent
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Abstract
A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the gate stack, including the silicide layer when the low-resistance gate stack is used in subsequent self-aligned contact etch processes.
Claims53
A gate structure for a semiconductor device, comprising:
- a gate oxide formed on a semiconductor substrate;
- a conductive gate formed on said gate oxide;
- a silicide layer formed on said conductive gate;
- and
- an etch protecting cap formed over a top surface of said silicide gate, said cap being sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure.
A method for forming a gate structure for a semiconductor device, comprising:
- forming a gate oxide on a semiconductor substrate;
- forming a conductive gate on said gate oxide;
- forming a silicide layer on said conductive gate by a salicide method;
- and
- forming an etch protective cap over a top surface of said silicide gate, said cap being sufficient to protect said conductive gate and silicide layer from being etched during a self-aligned contact etching process, employing said gate structure.
A method for forming features of a semiconductor device, comprising:
- forming a gate stack on a semiconductor substrate, said gate stack including an oxide layer provided on said substrate, a conductive layer over said oxide layer, a silicide layer over said conductive layer formed by a salicide process and a cap layer over said silicide layer;
- and
- providing an insulating layer over said substrate and said gate stack;
- and
- performing a self-aligned contact etch of said insulating layer using said gate stack to align said etch.
A method for forming a gate structure for a semiconductor device, comprising:
- forming an insulating layer over a substrate;
- masking said insulating layer to define an etching area on top of said insulating layer;
- etching said insulating layer at said etching area down to a top surface of said substrate to form an opening into said insulating layer;
- forming a gate oxide layer on said substrate at the bottom of said opening;
- depositing a polysilicon layer over said gate oxide layer;
- etching said polysilicon layer to form a polysilicon gate over said gate oxide layer;
- depositing a refractory metal over said polysilicon gate;
- converting said refractory metal to a silicide layer over said polysilicon gate;
- forming an etch protective cap over a top surface of said silicide layer;
- and
- etching away said insulating layer to leave a gate stack comprising said oxide layer, said polysilicon gate, said silicide layer, and said protective cap.
Dependencies are inferred from the claim text.