Pattern formation method, mask for exposure used for pattern formation, and method of manufacturing the same

A pattern formation method comprising:

• separating a memory cell pattern of each of a plurality of memory cells into a first pattern group provided at a predetermined position inside from an endmost portion of a cell and a second pattern group excluding said first pattern group;
• determining a mask size of said second pattern group such that said second pattern group secures a sufficient process margin relative to a given size and size accuracy;
• optimizing a mask size of said first pattern group according to a peripheral pattern environment such that said first pattern group has a desired size under a condition for determining said mask size of said second pattern group;
• forming a mask pattern of said memory cell according to said mask size of said second pattern group determined and said mask size of said first pattern group optimized;
• and
• forming said cell pattern on a semiconductor wafer, using said mask pattern.