FET circuit block with reduced self-heating

A silicon on insulator field effect transistor with reduced self-heating, comprising:

• a substrate;
• a buried oxide layer disposed on a portion of the substrate;
• a surface silicon layer disposed on the buried oxide layer, the surface silicon layer having an upper surface and an opposed lower surface;
• a source diffusion region formed in the surface silicon layer;
• a drain diffusion region formed in the surface silicon layer spaced apart from the source diffusion region by a source-to-drain separation distance;
• a channel region in the surface silicon layer disposed between the source diffusion region and the drain diffusion region, the channel region having a channel area;
• a gate structure disposed on the surface of the silicon surface layer region above the channel region adapted to modify the electrical conductance of the channel region, the gate structure having a gate length less than 0.15 microns;
• and
• a heat spreader coupled to the upper surface of the silicon surface layer of the drain diffusion region adjacent the channel region, the heat spreader subjoining a thermal transfer region of the drain diffusion region having an area greater than the channel area,
• the heat spreader configured to substantially reduce a thermal resistance associated with a flow of heat from the channel region to the substrate.

A high frequency integrated circuit comprising:

• a substrate;
• a digital logic circuit formed on the substrate including a first set of transistors having a gate length selected to perform a digital logic function at a clock cycle frequency;
• an on-chip memory circuit formed on the substrate;
• a regulatory circuit formed on the substrate having an output required for operation of the integrated circuit at the clock cycle frequency, the characteristics of the regulatory output being within an acceptable range at the clock cycle frequency for each transistor of a second set of transistors having a temperature rise associated with self-heating which is below a maximum temperature rise, each transistor of the second set of transistors comprising:
• a semiconductor layer disposed on the substrate, the semiconductor layer having an upper surface and an opposed lower surface;
• a source diffusion region formed in the semiconductor layer;
• a drain diffusion region formed in the semiconductor layer spaced apart from the source diffusion region by a source-to-drain separation distance;
• a gate structure residing on the upper surface of the semiconductor layer adapted to modify the electrical conductance of a channel region disposed between the source diffusion region and the drain diffusion region, the channel region having an associated channel area;
• one of the diffusion regions extended in area beyond the channel region to form a thermal transfer region having an area greater than the channel area;
• a heat spreader disposed on the upper surface of the semiconductor layer of the thermal transfer region, the heat spreader having an edge adjacent the channel region;
• the heat spreader and thermal transfer region configured to reduce a thermal resistance associated with a flow of heat from the channel region to the substrate by at least a factor of two.