Semiconductor circuit device having gate array area and method of making thereof
AssigneeKabushiki Kaisha Toshiba
InventorsYoshio Kaneko, Yoshihisa Tamura
Life of this patent
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Abstract
A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconductor substrate. An IP (Intellectual Property) region comprises a plurality of semiconductor devices formed on the semiconductor substrate and has a predetermined function. A first wiring layer is in the lower layer wiring region above the semiconductor substrate and a second wiring layer is above the IP region. A third wiring layer is in the upper wiring region of the gate array region. The third wiring layer is wider than the first and second wiring layers.
Claims19
A semiconductor integrated circuit having a lower-layered wiring region and an upper-layered wiring region on a semiconductor substrate, said semiconductor integrated circuit comprising:
- a gate array region on the semiconductor substrate;
- an IP (Intellectual Property) region including a plurality of semiconductor devices on the semiconductor substrate;
- a first wiring layer in the lower-layered wiring region above the gate array region;
- a second wiring layer above the IP region;
- and
- a third wiring layer above the upper-layered wiring region of the gate array region,
- wherein the third wiring layer has a width larger than the first and second wiring layers.
A semiconductor integrated circuit having a lower-layered wiring region and an upper-layered wiring region on a semiconductor substrate, said semiconductor integrated circuit comprising:
- a gate array region formed on the semiconductor substrate;
- an IP (Intellectual Property) region including a plurality of semiconductor devices on the semiconductor substrate and having a predetermined function;
- a first wiring layer in the lower-layered wiring region above the gate array region;
- a second wiring layer above the IP region;
- a third wiring layer in the upper-layered wiring region above gate array region;
- and
- a fourth wiring layer between the gate array region and the IP region,
- wherein the third and fourth wiring layers have widths larger than the first and second wiring layers.
A method of making a semiconductor integrated circuit device, comprising:
- forming a gate array region comprising a plurality of semiconductor device in a first region of a semiconductor substrate;
- forming a plurality of first wirings connected to the plurality of semiconductor devices formed in the first region;
- forming at least one IP (Intellectual Property) region comprising a plurality of semiconductor device in a second region of the semiconductor substrate;
- forming a plurality of second wirings connecting the plurality of semiconductor devices formed in the second region, the IP region having a predetermined function;
- and
- forming a plurality of third wirings connecting the plurality of first wirings to each other, the third wirings being wider than the first wirings and the second wirings.
Dependencies are inferred from the claim text.