US 2002/0118130 A1Published application

Method of generating matched capacitor arrays

AssigneeTexas Instruments Incorporated

InventorsSanjay S. Kulkarni, Senthil Kumar Subramanian, Ramachandra Venkateswara Sharma

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Abstract

An algorithmic procedure automatically generates layout of matched capacitor arrays used in A/D converters, D/A converters and programmable gain amplifiers, among other types of devices, using templates to define the style of the layout. Since each array can be generated from a particular template, multiple arrays associated with an IC can be optimized for different purposes to preserve silicon area. The automated technique allows fast and easy migration of an array layout from one process to another and eliminates the manual design work generally associated with capacitor array layout.

Claims23

Dependent claims

A method of automatically generating a matched capacitor array, the method comprising the steps of:

(a) accepting desired process design rules;
(b) accepting a capacitor array map file;
(c) accepting user specific rules;
(d) accepting unit capacitor cell x and y active area dimensions;
(e) generating a unit capacitor cell from the design rules, the array map file, the user specific rules, and the x and y active area dimensions;
(f) generating a master data file from the design rules, the array map file, the user specific rules, and the x and y active area dimensions;
(g) placing a plurality of unit capacitor cells in array fashion according to unit capacitor cell data and the master data file;
(h) mapping group numbers associated with the unit capacitor cells in each row to virtual numbers;
(i) connecting bottom capacitor plates of each unit capacitor cell to a horizontal control line determined by its mapped virtual number;
(j) connecting each horizontal control line to a respective main control line;
and
(k) connecting top capacitor plates of each unit capacitor cell to a main top plate line.

9 more elements

A method of automatically generating a matched capacitor array, the method comprising the steps of:

(a) providing a capacitor array map file comprising different groups of capacitors wherein each group other than a dummy capacitor group is associated with a distinct group number;
(b) determining a total number of distinct group numbers for each row of the matched capacitor array;
(c) associating each dummy capacitor group within the array with a distinct group number equal to the largest total number of distinct group numbers plus one;
(d) replacing each group within each row with an equivalent ascending number, wherein each ascending number within a row is determined by the distinct group numbers in step (b) and the distinct group number plus one in step (c), and further wherein the ascending numbers range from one to the largest total number of distinct group numbers plus one;
and
(e) implementing a matched capacitor array such that bottom plates associated with each distinct group of capacitors are connected to a respective control line, wherein the ascending number associated with each distinct group of capacitor cells defines the control line that is connected to the bottom plates.

3 more elements

Dependencies are inferred from the claim text.