Methods for manufacturing semiconductor devices and semiconductor devices

A method for manufacturing a semiconductor device, comprising:

• forming a gate dielectric layer on a semiconductor layer;
• forming a first conduction layer having a specified pattern on the gate dielectric layer;
• forming sidewall insulation layers on side walls of the first conduction layer;
• forming a source region and a drain region in the semiconductor layer;
• removing a part of the first conduction layer in a manner so that the gate dielectric layer is not exposed, to thereby form a recessed section on the first conduction layer between the sidewall insulation layers, wherein the removing a part of the first conduction layer is carried out after formation of the source region and the drain region;
• forming a second conduction layer in a portion of the recessed section;
• and
• forming an insulation layer in the recessed section on the second conduction layer.

A semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, a source region and a drain region, comprising:

• a second insulation layer formed on the gate electrode;
• sidewall insulation layers formed on side walls of the gate electrode;
• a first insulation layer formed on the sides of sidewall insulation layers,
• the gate electrode including a first conduction layer and a second conduction layer,
• the first conduction layer being formed on the gate dielectric layer,
• the second conduction layer being formed above the first conduction layer;
• a first through hole reaching the source region or the drain region formed in the first insulation layer;
• and
• a first contact layer formed in the first through hole,
• wherein, as the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, the first conduction layer has thickness that gradually becomes greater from a central section thereof toward the side walls thereof.

A semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, a source region and a drain region, comprising:

• a second insulation layer formed on the gate electrode;
• sidewall insulation layers formed on side walls of the gate electrode;
• a first insulation layer formed on the sides of sidewall insulation layers,
• the gate electrode including a first conduction layer and a second conduction layer,
• the first conduction layer being formed on the gate dielectric layer,
• the second conduction layer being formed above the first conduction layer;
• a first through hole reaching the source region or the drain region formed in the first insulation layer;
• a first contact layer formed in the first through hole,
• wherein, as the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, an end portion of the first conduction layer has a greater thickness as compared to a thickness thereof at a central section thereof.