Back to results
US 2002/0055247 A1Published application
Method for fabricating a memory cell configuration
AssigneeInfineon Technologies AG
InventorHans Reisinger
Life of this patent
Estimating the term…
Abstract
A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.
Claims4
A method for fabricating a memory cell configuration, which comprises:
- etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches;
- producing bit lines after channel regions have been produced;
- and
- subsequent to producing the bit lines, performing an etching step resulting in the isolation trenches penetrating more deeply into the semiconductor substrate.
1 more element
Dependencies are inferred from the claim text.