Method of power IC inspection
AssigneeMosel Vitelic, Inc.
InventorsKou-Liang Jaw, Jen-Te Chen
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Abstract
The present invention provides a method of power IC inspection to inspect whether an electrically-failed portion of power ICs results from photo resist peeling before or during source implantation. First, the metal layers on the power ICs are removed by the conventional etching process, and then the dielectric layers on the power ICs are removed by the conventional etching process. Finally, the semiconductor substrate is put into an acid solution containing chromium (Cr), so that a close contour is shown at each of the power ICs whose photo resist didn't peel during photolithography process and after source implantation.
Claims22
A method of power IC inspection for a number of power ICs manufactured on a semiconductor substrate, wherein said method is applied to inspect whether an electrically-failed portion of said power ICs results from photo resist peeling before or during source implantation, comprising:
- a. removing metal layers on said power ICs;
- b. removing dielectric layers on said power ICs;
- and
- c. putting said semiconductor substrate into an acid solution containing chromium (Cr);
- whereby a close contour is shown at each of said power ICs whose photo resist didn't peel before and during source implantation.
A method of power IC inspection for a number of power ICs manufactured on a semiconductor substrate, wherein said method is applied to inspect whether an electrically-failed portion of said power ICs results from photo resist peeling before or during source implantation, comprising:
- a. discovering hot spots on said semiconductor substrate by performing liquid crystal experiment and then laser-marking each of said electrically-failed portion of said power ICs according to said hot spots;
- b. removing metal layers on said power ICs;
- c. removing dielectric layers on said power ICs;
- d. putting said semiconductor substrate into a HNO3/HF/CrO3/H2O solution;
- whereby a close contour is shown at each of said power ICs whose photo resist didn't peel during photolithography process before and during source implantation, and no contour is shown at each of said power ICs whose photo resist peeled before or during source implantation.
Dependencies are inferred from the claim text.