Method for manufacturing semiconductor device
AssigneeHynix Semiconductor Inc.
InventorJae Hee Ha
Life of this patent
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Abstract
A method for manufacturing a semiconductor device is provided in which a polish stop point can be accurately measured for multiple layers formed of the same material. The method involves: depositing a first interlevel dielectric (ILD) film over a semiconductor substrate having steps; forming a planarization layer over the first ILD film; forming an insulation layer containing a metal over the planarization layer; forming a second ILD film over the insulation layer containing the metal; polishing the second ILD film, the insulation layer with the metal, and a portion of the planarization layer by chemical mechanical polishing (CMP), to planarize the semiconductor substrate, wherein a polish stop point is determined by measuring a variation of conductivity of byproducts from the CMP.
Claims16
A method for manufacturing a semiconductor device, the method comprising:
- depositing a first interlevel dielectric (ILD) film over a semiconductor substrate having at least one step;
- forming a planarization layer over the first ILD film;
- forming an insulation layer containing a metal over the planarization layer;
- forming a second ILD film over the insulation layer;
- polishing the second ILD film, the insulation layer, and a portion of the planarization layer using chemical mechanical polishing (CMP), to planarize the semiconductor substrate, wherein the polishing step produces an effluent;
- monitoring the effluent during the polishing step to determine a conductivity value;
- and
- terminating the polishing step when the conductivity value reaches a predetermined level.
A method for manufacturing a semiconductor device, the method comprising:
- depositing a first interlevel dielectric film over a semiconductor substrate having at least one step;
- forming a planarization layer over the first interlevel dielectric film;
- forming an insulation layer containing a metal over the planarization layer;
- polishing the insulation layer and a portion of the planarization layer by chemical mechanical polishing (CMP), to planarize the semiconductor substrate, wherein the polishing step produces an effluent;
- monitoring the effluent during the polishing step to determine a conductivity value;
- and
- terminating the polishing step when the conductivity value reaches a predetermined level.
A method for manufacturing a semiconductor device, the method comprising:
- forming a semiconductor substrate having a pattern of conductive material, the pattern producing at least one step;
- forming a planarization layer over the substrate and the pattern;
- forming an insulation layer over the planarization layer, the insulation layer comprising a metal oxide;
- polishing the substrate using a chemical mechanical polishing process to produce a planarized semiconductor substrate, the polishing step producing a liquid effluent, the effluent comprising polishing byproducts;
- monitoring the effluent during the polishing step to determine a conductivity value;
- and
- terminating the polishing step when the conductivity value reaches a predetermined level.
Dependencies are inferred from the claim text.