Circuit configuration having at least one nanoelectronic component and method for fabricating the component
AssigneeInfineon Technologies AG
InventorsTies Ramcke, Lothar Risch, Wolfgang Rosner
Life of this patent
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Abstract
At least one CMOS component which is configured in a semiconductor substrate is part of the inventive circuit assembly. An insulating layer is configured on the semiconductor substrate. The insulating layer covers the CMOS component. A nanoelectronic component is configured above the insulating layer. At least one conducting structure is configured in the insulating layer and serves to link the nanoelectronic component with the CMOS component. If several nanoelectronic components are provided, they are preferably grouped to nano-circuit blocks. Each of the nano-circuit blocks is so small that the RC times of their lines do not exceed 1 ns.
Claims12
A circuit configuration having at least one nanoelectronic component, the circuit configuration comprising:
- a semiconductor substrate;
- a CMOS circuit configured in said semiconductor substrate, said CMOS circuit including at least one CMOS component;
- an insulating layer that is configured on said semiconductor substrate and that covers said CMOS component;
- a first nanoelectronic component that is configured above said insulating layer;
- conductive structures that are configured in said insulating layer, at least one of said conductive structures connecting said first nanoelectronic component to said CMOS component;
- a plurality of nano-switching blocks configured above said insulating layer, each one of said plurality of said nano-switching blocks defined by a group of further nanoelectric components, each one of said plurality of said nano-switching blocks having lines with RC times that interconnect said further nanoelectric components of said one of said plurality of said nano-switching blocks, each one of said plurality of said nano-switching blocks having a size such that said RC times of said lines are not greater than 1 ns;
- a first drive circuit for said plurality of said nano-switching blocks, said first drive circuit defined by said CMOS circuit;
- and
- a plurality of second drive circuits, each one of said plurality of said nano-switching blocks being adjoined by a respective one of said plurality of said second drive circuits that is connected between said one of said plurality of said nano-switching blocks and said CMOS circuit;
- said conductive structures connecting said CMOS circuit to said plurality of said second drive circuits;
- one of said plurality of said second drive circuits combining said lines of said one of said plurality of said nano-switching blocks such that a number of said conductive structures that are connected to said one of said second drive circuits is less than a number of said lines of said one of said plurality of said nano-switching blocks.
A method for fabricating a circuit configuration, which comprises:
- providing a semiconductor substrate;
- using a CMOS method to produce at least one CMOS component in the semiconductor substrate;
- after producing the CMOS component, applying an insulating layer on the semiconductor substrate and covering the CMOS component with the insulating layer;
- producing a conductive structure in the insulating layer and connecting the conductive structure to the CMOS component;
- and
- using a nano-pattering technique to produce a nanoelectronic component above the insulating layer such that the nanoelectronic component is connected to the CMOS component by the conductive structure.
Dependencies are inferred from the claim text.