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US 2001/0042238 A1Published application
Semiconductor apparatus including bypass capacitor having structure for making automatic design easy, and semiconductor apparatus layout method
AssigneeNEC Corporation
InventorHirotaka Ishikawa
Life of this patent
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Abstract
A semiconductor apparatus, includes a semiconductor substrate, a first wiring, a second wiring and a capacitance cell. The first wiring is provided in the semiconductor substrate. The second wiring is provided in the semiconductor substrate. The capacitance cell includes a bypass capacitor connecting the first wiring to the second wiring.
Claims36
A semiconductor apparatus, comprising:
- a semiconductor substrate;
- a first wiring provided in said semiconductor substrate;
- a second wiring provided in said semiconductor substrate;
- and
- a capacitance cell, and
- wherein said capacitance cell includes a bypass capacitor connecting said first wiring to said second wiring.
3 more elements
A semiconductor apparatus, comprising:
- a semiconductor substrate;
- a function region provided in said semiconductor substrate, a predetermined function being performed in said function region;
- a first wiring provided in said semiconductor substrate;
- and
- a second wiring provided in said semiconductor substrate, and
- wherein said function region includes:
- a circuit cell having a circuit;
- and
- a capacitance cell, and
- wherein said capacitance cell includes a bypass capacitor connecting said first wiring to said second 15 wiring and said capacitance cell is arranged in a region where said circuit cell does not exist.
7 more elements
A semiconductor apparatus layout method, comprising:
- (a) arranging a first and second wirings on a semiconductor substrate;
- and
- (b) providing a capacitance cell, and
- wherein said capacitance cell includes a bypass capacitor connecting said first wiring to said second wiring.
1 more element
A semiconductor apparatus layout method, comprising:
- (a) arranging a circuit cell in a function region provided in a semiconductor substrate, wherein said circuit cell is cell indicating a region in which a circuit is mounted;
- (b) arranging first and second wirings on said semiconductor substrate;
- and
- (c) arranging a capacitance cell in a region where said circuit cell does not exist of said function region, and
- wherein said capacitance cell is a cell indicating a region in which a bypass capacitor is mounted, said bypass capacitor being electronically connected to a power supply wiring and a grounded wiring.
2 more elements
A semiconductor apparatus layout method, comprising:
- (d) arranging an I/O cell in an I/O region;
- (e) arranging a first capacitance cell in a portion where said I/O cell does not exist of said I/O region, wherein said first capacitance cell is a cell indicating a region in which a first bypass capacitance is mounted;
- (f) providing a power supply wiring and a grounded wiring, wherein said power supply wiring and said grounded wiring are electronically connected to said first bypass capacitance;
- (g) arranging a second capacitance cell in a region where an inner primitive region overlaps with said power supply wiring and said grounded wiring, wherein said second capacitance cell is a cell indicating a region in which a second bypass capacitance is mounted;
- (h) arranging a basic cell in said inner primitive region, wherein said basic cell is a cell indicating a region in which a predetermined circuit is mounted;
- and
- (i) arranging a third capacitance cell in a region where said basic cell and said second capacitance cell do not exist of said inner primitive region, wherein said third capacitance cell is a cell indicating a region in which a third bypass capacitance is mounted.
4 more elements
A computer readable recording medium for recording a program for a process, comprising:
- (a) arranging a first and second wirings on a semiconductor substrate;
- and
- (b) providing a capacitance cell, and
- wherein said capacitance cell includes a bypass capacitor connecting said first wiring to said second wiring.
1 more element
A computer readable recording medium for recording a program for a process, comprising:
- (a) arranging a circuit cell in a function region provided in a semiconductor substrate, wherein said circuit cell is cell indicating a region in which a circuit is mounted;
- (b) arranging first and second wirings on said semiconductor substrate;
- and
- (c) arranging a capacitance cell in a region where said circuit cell does not exist of said function region, and
- wherein said capacitance cell is a cell indicating a region in which a bypass capacitor is mounted, said bypass capacitor being electronically connected to a power supply wiring and a grounded wiring.
2 more elements
A computer readable recording medium for recording a program for a process, comprising:
- (d) arranging an I/O cell in an I/O region;
- (e) arranging a first capacitance cell in a portion where said I/O cell does not exist of said I/O region, wherein said first capacitance cell is a cell indicating a region in which a first bypass capacitance is mounted;
- (f) providing a power supply wiring and a grounded wiring, wherein said power supply wiring and said grounded wiring are electronically connected to said first bypass capacitance;
- (g) arranging a second capacitance cell in a region where an inner primitive region overlaps with said power supply wiring and said grounded wiring, wherein said second capacitance cell is a cell indicating a region in which a second bypass capacitance is mounted;
- (h) arranging a basic cell in said inner primitive region, wherein said basic cell is a cell indicating a region in which a predetermined circuit is mounted;
- and
- (i) arranging a third capacitance cell in a region where said basic cell and said second capacitance cell do not exist of said inner primitive region, wherein said third capacitance cell is a cell indicating a region in which a third bypass capacitance is mounted.
4 more elements
Dependencies are inferred from the claim text.