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US 2001/0040816 A1Published application
Reduced leakage DRAM storage unit
AssigneeMicron Technology, Inc.
InventorsZhigiang (Jeff) Wu, Randhir PS Thakur, Alan Reinberg, Kirk Prall
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Abstract
The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.
Claims31
A memory cell, comprising:
- a storage node;
- a switching device for controlling access to said storage node;
- and
- a diode between said switching device and said storage node.
1 more element
A solid state memory cell, comprising:
- a storage capacitor;
- a transistor having first and second terminals defining a conduction path and a control terminal;
- and
- a junction fabricated between said storage capacitor and one of said first and second terminals, said junction establishing a potential barrier having a value dependent upon the value of a charge applied to said control terminal of said transistor.
1 more element
An array of memory cells, comprising:
- a plurality of memory cells, each cell comprised of:
- a storage capacitor;
- a transistor having first and second terminals defining a conduction path and a control terminal;
- and
- a junction positioned between said storage capacitor and said first terminal;
- a plurality of column lines connected to said second terminals;
- a plurality of row lines connected to said control terminals;
- a plurality of sense amplifiers connected between said column lines;
- and
- a plurality of precharge circuits connected between said column lines.
7 more elements
A memory device, comprising:
- an array of memory cells;
- read control logic for reading information from said array;
- write control logic for writing information to said array, and wherein said array is comprised of:
- a plurality of memory cells, each cell comprised of:
- a storage capacitor;
- a transistor having first and second terminals defining a conduction path and a control terminal;
- and
- a junction positioned between said storage capacitor and said first terminal;
- a plurality of column lines connected to said second terminals;
- a plurality of row lines connected to said control terminals;
- a plurality of sense amplifiers connected between said column lines;
- and
- a plurality of precharge circuits connected between said column lines.
10 more elements
A system, comprising:
- a processor;
- an array of memory cells connected to said processor;
- read control logic for reading information from said array;
- write control logic for writing information to said array, and wherein said array is comprised of a plurality of memory cells, each cell comprised of:
- a storage capacitor;
- a transistor having first and second terminals defining a conduction path and a control terminal;
- and
- a junction positioned between said storage capacitor and said first terminal;
- a plurality of column lines connected to said second terminals;
- a plurality of row lines connected to said control terminals;
- a plurality of sense amplifiers connected between said column lines;
- and
- a plurality of precharge circuits connected between said column lines.
10 more elements
A method of controlling charge transfer to and from a storage node through a switching device, comprising the steps:
- placing a charge on a control terminal of the switching device to access the storage node, said charge establishing a first potential barrier between a conduction terminal of the switching device and said storage node;
- and
- removing said charge from said control terminal to end access to said storage node, resulting in a second potential barrier between said conduction terminal and said storage node that is larger than said first potential barrier.
Dependencies are inferred from the claim text.