Method and apparatus for forming a junctionless antifuse

An antifuse structure, formed in an integrated circuit, comprising:

• a top conductor layer;
• a bottom conductor layer,
• a programming layer positioned between the top and bottom conductor layers;
• a first conducting layer on the bottom conductor layer;
• and
• an insulator disposed between the first conducting layer and a semiconductor substrate.

A method for selectively forming an antifuse in an integrated circuit comprising the steps of:

• forming a first conducting layer on an insulator, which is supported by a semiconductor substrate;
• forming a refractory metal silicide layer on the first conducting layer;
• forming a bottom conductor layer on the refractory metal silicide layer;
• forming a programming layer on the bottom conductor layer;
• and
• forming a top conductor layer on the programming layer.

An antifuse structure, formed in an integrated circuit, comprising:

• a top conductor layer;
• a bottom conductor layer;
• a programming layer, positioned between the top and bottom conductor layers;
• a refractory metal silicide layer, on the bottom conductor layer;
• a first conducting layer, on the refractory metal silicide layer;
• and
• an insulator, disposed between the first conducting layer and a semiconductor substrate.

A method for selectively forming an antifuse in an integrated circuit comprising the steps of:

• forming a bottom conductor layer on an insulator, which is supported by a semiconductor substrate;
• forming a programming layer on the bottom conductor layer;
• and
• forming a top conductor layer on the programming layer.

An antifuse structure, formed in an integrated circuit, comprising:

• a top conductor layer;
• a bottom conductor layer;
• a programming layer, positioned between the top and bottom conductor layers;
• and
• an insulator, positioned between the bottom conductor layer and a semiconductor substrate.