Field effect transistor structure with self-aligned raised source/drain extensions

A field effect transistor, comprising:

• a substrate having a recess in a surface thereof, the recess having bottom portion and tapered sidewalls, the tapered sidewall surfaces forming an obtuse angle with respect to the bottom portions of the recess;
• a gate dielectric layer disposed superjacent the bottom portion of the recess and adjacent the tapered sidewalls;
• a gate electrode overlying the gate dielectric layer;
• and
• source/drain terminals disposed in the substrate in alignment with a pair of laterally opposed gate electrode sidewalls;
• wherein the source/drain terminals have an extension which extends downwardly, from approximately the surface of the substrate, along the sidewalls of the recess.

A field effect transistor, comprising:

• a substrate having a recess in a surface thereof, the recess having a curvilinear shape;
• a gate dielectric layer disposed superjacent the curvilinear recess;
• a gate electrode overlying the gate dielectric layer;
• and
• source/drain terminals disposed in the substrate in alignment with a pair of laterally opposed gate electrode sidewalls;
• wherein the source/drain terminals have an extension which extends downwardly, from approximately the surface of the substrate, along the curvilinear sides of the recess.

A method of making a microelectronic device, comprising:

• forming a first layer over a substrate;
• forming openings in the first layer, the openings exposing a portion of the substrate, the openings having substantially vertical sidewalls;
• forming a first spacer adjacent the sidewalls of the first layer openings;
• forming a second spacer adjacent the first spacer;
• etching a portion of the exposed substrate;
• removing the second spacer;
• forming a dielectric layer superjacent the exposed portions of the substrate;
• forming an electrode superjacent the dielectric layer;
• and
• removing the first layer.

A method of forming a field effect transistor, comprising:

• depositing an etch stop layer and a damascene layer over a silicon substrate;
• removing portions of the damascene and etch stop layers to expose portions of the silicon, and form sidewalls in the damascene and etch stop layers;
• forming a first spacer layer along the sidewalls of the damascene layer and the etch stop layer;
• etching the exposed silicon;
• removing the second spacer;
• forming a gate dielectric layer superjacent the etched silicon;
• and depositing a gate electrode layer over the damascene and gate dielectric layers;
• planarizing the gate electrode layer so as to form a gate electrode;
• removing the damascene, second spacer, and etch stop layers;
• and
• forming source/drain terminals self-aligned to the gate electrode.

A method of forming a field effect transistor, comprising:

• depositing an etch stop layer and a damascene layer over a silicon substrate;
• removing portions of the damascene and etch stop layers to expose portions of the silicon, and form sidewalls in the damascene and etch stop layers;
• forming a first spacer layer along the sidewalls of the damascene layer and the etch stop layer, and a second spacer adjacent the first spacer layer;
• oxidizing the exposed silicon;
• etching the exposed oxidized silicon;
• removing the second spacer;
• forming a gate dielectric layer superjacent the etched silicon;
• and depositing a gate electrode layer over the damascene and gate dielectric layers;
• planarizing the gate electrode layer so as to form a gate electrode;
• removing the damascene, second spacer, and etch stop layers;
• and
• forming source/drain terminals self-aligned to the gate electrode.