PIP capacitor for split-gate flash process

A method of forming a PIP (Poly-Interpoly-Poly) capacitor with high capacitance in a split-gate flash memory cell comprising the steps of:

• providing a semiconductor substrate having a gate region and a capacitor region, and a first gate dielectric layer formed thereon;
• depositing a first polysilicon layer to form the floating gate of said memory cell in said gate region, and to form the first electrode of said PIP capacitor in said capacitor region;
• forming a poly-oxide layer over said first polysilicon layer;
• forming a second gate dielectric layer over said substrate including said gate region and said capacitor region;
• ion implanting said first polysilicon layer in said capacitor region to control dopant level in said first electrode of said PIP capacitor;
• forming a third gate dielectric layer over said substrate including over said poly-oxide layer over said floating gate, and over said first electrode of said PIP capacitor;
• and
• depositing a second polysilicon layer to form the control gate of said memory cell in said gate region, and to form the second electrode of said PIP capacitor in said capacitor region on said substrate.

A method of forming a PIP (Poly-Interpoly-Poly) capacitor with high capacitance in a split-gate flash memory cell comprising the steps of:

• providing a semiconductor substrate having a gate region and a capacitor region;
• forming a first gate dielectric layer over said substrate having a gate region and a capacitor region;
• forming a first polysilicon layer over said first gate dielectric layer over said gate region and over said capacitor region;
• forming a nitride layer over said first polysilicon layer;
• forming and patterning a first photoresist layer over said nitride layer to have an opening corresponding to a region on the substrate where a floating gate is to be formed;
• etching said nitride layer through said opening in said first photoresist layer to expose a portion of underlying said first polysilicon layer;
• ion implanting said portion of said underlying first polysilicon layer through said opening in said nitride layer;
• removing said first photoresist layer;
• performing oxidization through said opening in said nitride layer, thus forming a poly-oxide layer over said portion of said underlying first polysilicon layer;
• removing said nitride layer, thus exposing portions of first polysilicon layer not covered by said poly-oxide layer;
• forming and patterning a second photoresist layer to protect an exposed portion of said first polysilicon layer corresponding to said capacitor region where said PIP capacitor is to be formed;
• etching said first polysilicon layer to form said floating gate protected by said poly-oxide layer and to form a first electrode of said PIP capacitor protected by said second photoresist layer in said capacitor region;
• forming a second gate dielectric layer over said substrate including said gate region and said capacitor region;
• forming and patterning a third photoresist layer to form an opening over said first electrode of said PIP capacitor in said capacitor region;
• ion implanting said first polysilicon layer through said opening in said capacitor region to adjust dopant level in
• said first electrode of said PIP capacitor;
• removing said third photoresist layer;
• performing an oxide dip to remove said second gate dielectric layer from said substrate;
• forming a third gate dielectric layer over said substrate including over said poly-oxide layer over said floating gate, and over said first electrode of said PIP capacitor;
• depositing a second polysilicon layer over said third gate dielectric to form a control gate in said gate region, and to form a second electrode of said PIP capacitor in said capacitor region of said split-gate flash memory cell;
• and
• forming a silicide layer over said control gate in preparation for forming a word-line over said control gate.