Semiconductor device manufacturing system and method of manufacturing semiconductor devices

A semiconductor device manufacturing system comprising:

• a manufacturing line which manufactures a wafer with a plurality of semiconductor memories provided therein in a grid-like arrangement by a predetermined manufacturing device;
• a wafer tester which tests said semiconductor memories for electric characteristics thereof;
• a trimming device which determines a redundancy address for a redundancy memory of each semiconductor memory and blows fuses corresponding to said redundancy address;
• a wafer test information storage device which stores said redundancy address and position information on said wafer that is associated with said redundancy address;
• a package assembling device which divides said wafer into respective ones of said semiconductor memories to produce semiconductor memories each sealed in a package;
• a product tester which tests each semiconductor memory after the division for its electric characteristics and reads a replacement address;
• a position estimating device which estimates position information by comparing said read replacement address with said redundancy address;
• a product test information storage device which stores a second test result outputted from said product tester and said position information detected by said position estimating device that is associated with said second test result;
• and
• a failure distribution mapping device which maps the distribution of failures by associating said second test result with said position information;
• wherein a cause of failures is determined based on said distribution of failures.

A semiconductor device manufacturing system comprising:

• a manufacturing line which manufactures a wafer with a plurality of semiconductor memories provided therein in a grid-like arrangement by a predetermined manufacturing device;
• a wafer tester which tests said semiconductor memories for electric characteristics thereof;
• a trimming device which determines a replacement address for a redundancy memory of each semiconductor memory and blows fuses corresponding to said replacement address;
• a position information storage device which stores said replacement address and position information on said wafer that is associated with said replacement address;
• a package assembling device which divides said wafer into respective ones of said semiconductor memories to produce semiconductor memories each sealed in a package;
• a product tester which tests each semiconductor memory for its electric characteristics and reads a replacement address;
• a position estimating device which estimates position information by comparing said read replacement address with said replacement address stored in said position information storage device;
• a product test information storage device which stores a first test result outputted by said wafer tester, a second test result outputted from said product tester and said position information on said wafer estimated by said position estimating device in association with one another;
• and
• a failure distribution mapping device which maps, based on said first test result, said second test result and said position information, the distribution of failures by combining position information of those semiconductor memories determined to be faulty by said wafer tester and position information of those semiconductor memories determined to be faulty by said product tester;
• wherein a cause of failures is determined based on said distribution of failures.

A semiconductor device manufacturing system for estimating the location of a cause of a failure based on a test result of a manufactured semiconductor device comprising:

• a position information reading device which electronically reads chip data previously written in a predetermined circuit of said semiconductor device after this semiconductor device has been sealed into a package;
• a position information extracting device which extracts a lot number of said semiconductor device in a wafer process, a wafer number of a wafer in said lot and position information on said wafer based on said chip data;
• and
• a failure cause determining device which determines a cause of a failure which has occurred after division of said wafer into chips by combining respective test results before and after said division into a single distribution of failures.

A failure analyzing device comprising:

• a chip position analyzing device which estimates a position of chip on a wafer;
• a failure distribution mapping device which maps a distribution of semiconductor chips which have become faulty;
• and
• a failure cause determining device which determines a cause of a failure from said distribution.

A method of manufacturing semiconductor devices comprising:

• a wafer step which forms semiconductor devices in a wafer through a plurality of processing steps;
• a wafer test step which tests said semiconductor devices in a wafer state;
• an assembling step which cuts said wafer into chips of said semiconductor devices and seals only those of said chips which have passed said test respectively into packages;
• an assembly test step which tests said chips in a packaged state and which selects non-defective chips;
• a chip data reading step which electronically reads chip data previously stored in a predetermined circuit of each of those semiconductor devices which have been determined as faulty in said assembly test step;
• and
• a position information extracting step which extracts, based on said chip data, position information which comprises a lot number of the relevant semiconductor device in said wafer step, a wafer number of the relevant wafer in this lot and coordinates of the relevant chip in this wafer.