US 2001/0026486 A1 · Semiconductor memory production system and semiconductor memory production method

Abstract

A semiconductor memory production system is provided, capable of holding the data necessary for process analysis for each lot in chronological order using a small amount of information, and which enables production management based on data that has been stored previously without performing new measurements. The semiconductor memory production system comprises: an LSI tester 1 that tests semiconductor memory and outputs the addresses of memory cells for each chip and a pass/fail bitmap corresponding to these addresses, and a process defect estimating device 34 that extracts the bit addresses of fail bits from the bitmap, and determines replacement addresses of word lines and bit lines to be replaced by redundant word lines and redundant bit lines in the redundant memory section, and estimates process defects from statistical analysis of the distribution condition of each chip on each wafer. Through this estimated result, feedback to the manufacturing line/process step prevents from producing defects frequently.

Claims12

Dependent claims

A semiconductor memory production system comprising:

a wafer manufacturing line for manufacturing a plurality of semiconductor memory chips on a wafer using a plurality of kinds of wafer manufacturing equipment,
a wafer tester for testing the electrical characteristics of said chips;
a replacement address decision device for determining replacement addresses in a redundant memory section installed in said semiconductor memory based on the test results of said wafer tester;
and
an estimation section for estimating the cause of failures based on results of statistical processing of said replacement addresses,
wherein wafer manufacturing equipment causing failures is identified in said wafer manufacturing line and the cause of the failures is removed.

3 more elements

A semiconductor memory production method comprising:

a wafer processing step for forming a semiconductor memory on a wafer through a plurality of processes;
a wafer testing step for testing said wafer in the wafer state to select non5 defective products;
a bit map outputting step for outputting, as a result of said testing, the addresses of memory cells of each semiconductor memory and a bit map showing the pass and fail determination of the addresses;
a replacement address decision step that extracts the bit address of a fail bit from said bitmap and, based on this bit address, determines a replacement word line and/or bit line address to be replaced with a redundant word line and/or redundant bit line in a redundant memory section installed in said semiconductor memory;
and
a process defect estimation step for estimating process defects by statistical analysis based on the replacement number of the replaced word lines or/and bit lines for each semiconductor memory, obtained based on said replacement addresses, or by the statistical analysis of the distribution states of the semiconductor memory in each wafer.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory production system and semiconductor memory production method

Life of this patent

Semiconductor memory production system and semiconductor memory production method

Life of this patent

Abstract

Claims12