Semiconductor integrated circuit and wiring method
AssigneeNEC Corporation
InventorSumio Kuwabara
Life of this patent
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Abstract
In the semiconductor integrated circuit of the present invention, an n-channel MOS transistor and a p-channel MOS transistor, which are a plurality of circuit components that have been designed beforehand, are connected by means of wiring as a portion of a configuration content. Both a power supply potential wiring layer for supplying a power supply potential to circuit components and a ground potential wiring layer for supplying a ground potential to the circuit components are provided between the wiring used to connect together nodes inside the circuit components and the wiring between circuit components so as to generally cover the circuit components.
Claims12
A wiring method of a semiconductor integrated circuit that is formed as a portion of a configuration content by connecting a plurality of circuit components that have been designed beforehand;
- comprising a step in which both a power supply potential wiring layer for supplying a power supply potential to the circuit components and a ground potential wiring layer for supplying the ground potential to the circuit components are provided between a wiring layer used for interconnections of nodes inside the circuit components and other wiring layers so as to generally cover the circuit components.
A semiconductor integrated circuit comprising:
- a plurality of circuit components that have been designed beforehand and that are formed as a portion of a configuration content by being connected by wiring;
- a wiring layer that is used for connecting together nodes inside the circuit components;
- a power supply potential wiring layer for supplying a power supply potential to the circuit components;
- and
- a ground potential wiring layer for supplying the ground potential to the circuit components;
- wherein both said power supply potential wiring layer and said ground potential wiring layer are provided between said wiring layer that is used for connecting together nodes inside the circuit components and other wiring layers so as to generally cover said circuit components.
Dependencies are inferred from the claim text.