High density vertical sram cell using bipolar latchup induced by gated diode breakdown
AssigneeMicron Technology, Inc.
InventorsWendell P. Noble JR., Leonard Forbes
Life of this patent
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Abstract
Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
Claims58
A memory cell, comprising a gated diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latchup of said diode.
A circuit for storing information as one of at least two possible bistable current states, comprising
- at least one p-n-p-n transistor;
- and
- a transistor gate in connection with the central n-p junction of said p-n-p-n transistor.
A SRAM cell, comprising:
- a p-n-p-n transistor having a first p-n junction, a first n-p junction and a second p-n junction;
- and
- a gate in contact with the first n-p junction, wherein said gate is connected to a voltage source for producing latch-up in said p-n-p-n transistor.
A SRAM array, comprising
- a substrate;
- a plurality of vertical p-n-p-n transistors;
- a first set of isolation trenches between said p-n-p-n transistors for isolating said transistors in a first direction;
- a second set of isolation trenches orthogonal to said first set of trenches for isolating said transistors in a second direction;
- and
- gate lines in one of said first or second sets of trenches and connecting the central p-n junctions of at least some of said plurality of transistors.
A computer system, comprising
- a processor;
- and
- a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising a gated p-n-p-n diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said p-n-p-n diode.
A method of forming a memory cell for storing information as one of at least two possible bistable current states, the method comprising the following steps:
- providing a semiconductor substrate;
- providing doped silicon regions in the following doping profile:
- p, n, p and n, to form a vertical p-n-p-n diode;
- and
- forming a p+ polysilicon gate in connection with the central n-p region of said diode.
A semiconductor processing method of forming CMOS static access memory within a semiconductor substrate, the method comprising the following steps:
- providing a semiconductor substrate;
- defining an array trench within said substrate;
- providing doped silicon in said trench in the following doping profile:
- p, n, p and n;
- defining a first set of trenches in said doped silicon by directional etching to a depth at least sufficient to expose the buried p-type layer;
- defining a second set of trenches orthogonal to said first set of trenches by directional etching to a depth at least sufficient to expose the buried p-type layer;
- growing a gate oxide layer on the sidewalls of said first set of trenches;
- and
- defining a p-type polysilicon gate within one of said trenches and in contact with the n and p regions of said doped silicon.
A semiconductor processing method of forming CMOS static access memory within a semiconductor substrate, the method comprising the following steps:
- providing a semiconductor p-type substrate;
- defining an array trench within said substrate;
- providing doped silicon in said trench in the following doping profile:
- n, p, n, p and n;
- defining a first set of trenches in said doped silicon by directional etching to a depth at least sufficient to expose the buried lowermost p-type layer;
- defining a second set of trenches orthogonal to said first set of trenches by directional etching to a depth at least sufficient to expose the buried n-type layer;
- growing a gate oxide layer on the sidewalls of said second set of trenches;
- depositing oxide to fill the first and second sets of trenches up to past the bottom of the lowermost n-type layer;
- depositing a p-type polysilicon layer within the second set of trenches;
- and
- removing said polysilicon layer, while leaving remaining polysilicon as gate material on one sidewall of each trench of said second set of trenches.
A method of storing a binary logic value comprising:
- inducing latch-up in a gated diode.
A method of forming a circuit for storing information as one of at least two possible stable current states, the method comprising the following steps:
- providing a semiconductor substrate;
- providing doped silicon regions to form a multi-region vertical thyristor having at least four regions;
- forming at least one polysilicon gate overlying a junction of said multi-region vertical thyristor;
- and
- connecting said at least one polysilicon gate to a voltage source for producing latch-up in said multi-region vertical thyristor.
Dependencies are inferred from the claim text.