Semiconductor circuit design methods, semiconductor processing methods and integrated circuitry

A semiconductor processing method comprising:

• forming a masking layer over a substrate, the masking layer defining a plurality of conductive lines which are to be etched, some of the defined conductive lines constituting active gate lines positioned over substrate active areas, other of the defined conductive lines constituting space-compensating conductive lines at least some of which having portions positioned over isolation oxide areas and being defined by the masking layer only to satisfy a spacing constraint which describes a desired active gate line-to-gate line spacing;
• and
• etching to form the plurality of conductive lines through the masking layer.

A semiconductor processing method comprising forming a plurality of conductive lines over a substrate, some of the conductive lines providing transistor gate lines over substrate active areas, other of the conductive lines being formed only to satisfy a spacing constraint which describes a desired spacing between the transistor gate lines.

Integrated circuitry comprising:

• a semiconductive substrate comprising active areas;
• a plurality of conductive lines disposed over the semiconductive substrate, some of the conductive lines providing transistor gate lines over said active areas, other of the conductive lines being disposed only to satisfy a spacing constraint which describes a desired spacing between the transistor gate lines.

A semiconductor processing method comprising:

• forming a plurality of conductive lines over substrate active areas, said plurality of conductive lines comprising (a) edge lines which have no immediate conductive line neighbor on only one side thereof within a selected distance, (b) isolated lines which have no immediate conductive line neighbor on either side thereof within the selected distance, and (c) center lines which have immediate conductive line neighbors on each side thereof within the selected distance;
• and
• for the edge lines and isolated lines, forming additional space-compensating structures proximate at least some of the edge and isolated lines and spaced-apart from the side or sides, respectively, which have no immediate conductive line neighbor within the selected distance, and wherein the additional space-compensating structures have portions which are formed no further away from their associated edge or isolated line than the selected distance.

A semiconductor processing method comprising:

• defining a plurality of conductive lines which are to be disposed over substrate active areas, said plurality of conductive lines comprising (a) edge lines which have no immediate conductive line neighbor on only one side thereof within a selected distance, (b) isolated lines which have no immediate conductive line neighbor on either side thereof within the selected distance, and (c) center lines which have immediate conductive line neighbors on each side thereof within the selected distance, the center lines being defined to have, when etched, generally uniform associated channel lengths;
• and
• for the edge lines and isolated lines, defining additional space-compensating structures proximate at least some of the edge and isolated lines and spaced-apart from the side or sides, respectively, which have no immediate conductive line neighbor within the selected distance, the additional space-compensating structures being positioned to define, when etched, channel lengths for the some of the edge and isolated lines which are substantially the same as the generally uniform channel lengths of the center lines.

A semiconductor processing method comprising manufacturing a plurality of integrated circuitry devices in accordance with a design rule which provides for the addition of added space-compensating structures within a predetermined distance laterally proximate individual transistor gate lines when there would not, otherwise, be a structure within the predetermined distance.