Back to results
US 2001/0011362 A1Published application
Semiconductor layout design method and apparatus
AssigneeNEC Corporation
InventorHiroko Yoshinaga
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNEC Corporation
InventorHiroko Yoshinaga
Estimating the term…
According to a semiconductor device design method and apparatus of the present invention, a semiconductor device with homogenous wiring densities throughout the entire layout, and with uniform etching, is provided. In order to facilitate homogenous levels of wiring density and uniform etching within the design of the semiconductor layout after the layout has been configured (S1) using an automated layout system, certain regions of the layout are tested (S2). Once regions of low density have been determined (S3), dummy terminals are formed on power and ground lines (S11, S12). These dummy terminals are then interconnected with supplemental wiring (S13 to S16) so that the density of the selected region is brought within a predetermined allowable range.
A semiconductor layout design method of designing semiconductor layouts with homogenous levels of wiring density, comprising:
A semiconductor layout design method of designing semiconductor layouts with homogenous levels of wiring density, comprising:
An apparatus for designing semiconductor layouts with homogenous levels of wiring density, comprising:
An apparatus for designing semiconductor layouts with homogenous levels of wiring density, comprising:
Dependencies are inferred from the claim text.