Method for monitoring step height of epitaxial layer of CMOS device

A method for monitoring step height of an epitaxial layer of a CMOS device, comprising:

• S1:
• determining a CMOS device to be monitored and fabricating a measurement reference device,
• active area and shallow trench isolation structures of the measurement reference device being the same as those of the CMOS device to be monitored,
• polysilicon lines being formed on the active area and shallow trench isolation structures of the measurement reference device,
• the polysilicon lines on the active area structures of the measurement reference device having the same front-rear length and the same left-right width,
• the polysilicon lines on the shallow trench isolation structures of the measurement reference device having the same front-rear length and the same left-right width,
• the polysilicon lines on the active area structures of the measurement reference device being connected in series through back-end connecting lines to obtain a first polysilicon line string,
• the polysilicon lines on the shallow trench isolation structures of the measurement reference device being connected in series through back-end connecting lines to obtain a second polysilicon line string;
• S2:
• applying test voltage U respectively to the first polysilicon line string and the second polysilicon line string of the measurement reference device to respectively measure current I1 flowing through the first polysilicon line string and current I2 flowing through the second polysilicon line string;
• S3:
• performing calculation to obtain step height SH of an epitaxial layer of the measurement reference device according to the following formula:
• SH
• =
• ρ
• *
• L
• ⁢
• 2
• *
• I
• ⁢
• 2
• /
• (
• W
• ⁢
• 2
• *
• U
• )
• -
• ρ
• *
• L
• ⁢
• 1
• *
• I
• ⁢
• 1
• /
• (
• W
• ⁢
• 1
• *
• U
• )
• where ρ is the resistivity of polysilicon, L2 is the front-rear length of the polysilicon lines on the shallow trench isolation structures of the measurement reference device, W2 is the left-right width of the polysilicon lines on the shallow trench isolation structures of the measurement reference device, L1 is the length of the polysilicon lines on the active area structures of the measurement reference device, and W1 is the left-right width of the polysilicon lines on the active area structures of the measurement reference device;
• and
• S4:
• using the step height of the epitaxial layer of the measurement reference device as step height of an epitaxial layer of the CMOS device to be monitored.