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US 12,772,433 B2Granted
Single gate three-dimensional (3D) dynamic random-access memory (DRAM) devices
AssigneeApplied Materials, Inc.
InventorsChang Seok Kang, Sung-Kwan Kang
Life of this patent
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Abstract
A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.
Claims20
A memory cell array, comprising:
- a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising:
- a first spacer layer extending in a second direction that is orthogonal to the first direction;
- a second spacer layer extending in the second direction, disposed below the first spacer layer in the first direction;
- an active region disposed directly above the second spacer layer and below the first spacer layer in the first direction;
- a cell transistor having a single gate disposed between the first spacer layer and the second spacer layer in the first direction;
- and
- a cell capacitor having a bottom electrode layer between the first spacer layer and the second spacer layer in the first direction, wherein the bottom electrode layer is electrically connected to the active region.
4 more elements
A method of forming cell transistors in a semiconductor memory device, comprising:
- depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising a thicker channel layer, a thicker sacrificial layer over the thicker channel layer, a thinner channel layer over the thicker sacrificial layer, and a thinner sacrificial layer over the thinner channel layer stacked in a first direction;
- forming a transistor slit through the stacking mold in the first direction;
- forming first recesses in the thicker sacrificial layers and second recesses in the thinner sacrificial layers from sidewalls of the transistor slit;
- partially filling the first recesses and fully filling with the second recesses with a first insulator layer from the sidewalls of the transistor slit;
- and
- removing the first insulator layer on the sidewalls of the transistor slit and within the first recesses.
3 more elements
A method of forming cell capacitors in a semiconductor memory device, comprising:
- depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising a thicker channel layer, a thicker sacrificial layer over the thicker channel layer, a thinner channel layer over the thicker sacrificial layer, and a thinner sacrificial layer over the thinner channel layer stacked in a first direction;
- forming a transistor slit through the stacking mold in the first direction;
- forming first openings in the thicker sacrificial layers and second openings in thinner sacrificial layers from sidewalls of the capacitor slits;
- partially filling the first openings and fully filling the second openings with a spacer layer from the sidewalls of the capacitor slits;
- and
- removing the spacer layer on the sidewalls of the capacitor slits and within the first openings.
3 more elements
Dependencies are inferred from the claim text.