Carrier substrate for SOI structure and associated manufacturing method

A silicon-on-insulator (SOI) structure, comprising:

• a working layer disposed on a dielectric layer, the dielectric layer disposed on a carrier substrate, the carrier substrate comprising monocrystalline silicon and having a front face and a back face, the carrier substrate further comprising:
• a surface region extending from the front face to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs);
• an upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm;
• and
• a lower region extending between the upper region and the back face, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3.

An electronic component for radiofrequency or low-power logic application, comprising:

• a silicon-on-insulator (SOI) structure including a working layer disposed on a dielectric layer, the dielectric layer disposed on a carrier substrate, the carrier substrate comprising monocrystalline silicon and having a front face and a back face, the carrier substrate further comprising:
• a surface region extending from the front face to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs);
• an upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm;
• and
• a lower region extending between the upper region and the back face, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3;
• and
• at least one transistor disposed on and/or in the working layer of the SOI structure.

A method for manufacturing a carrier substrate, the method comprising:

• a) providing a substrate comprising monocrystalline silicon, the substrate having an interstitial oxygen content between 12E17 Oi/cm3 and 16E17 Oi/cm3 and a resistivity higher than 500 ohm·cm;
• b) applying a first heat treatment at a temperature between 1150° C. and 1250° C., under a neutral or reducing atmosphere, for a duration longer than or equal to 30 min, to form a surface region and an upper region in the substrate, the surface region extending from a front face of the substrate to a depth of between 800 nm and 2 microns, the surface region having fewer than ten crystal-originated particles (COPs), the upper region extending from the front face to a depth of between a few microns and 40 microns, the upper region having an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm;
• and
• c) applying a second heat treatment comprising a first sequence of annealing at a temperature between 600° C. and 900° C., and a second sequence of annealing at a temperature between 950° C. and 1100° C., to form a lower region in the substrate, the lower region extending between the upper region and a back face of the substrate, the lower region having a micro-defect concentration higher than or equal to 1E8/cm3.