Small dummy poly pattern insertion in small border regions

A method comprising:

• identifying a plurality of intellectual property (IP) blocks in an integrated circuit;
• identifying border regions in the integrated circuit, the border regions being outside the plurality of IP blocks and including at least one small border region and at least one large border region, wherein the small border region has a width in a first horizontal direction and a length in a second horizontal direction perpendicular to the first horizontal direction, and at least one of the width and the length is between a small border region dimension lower limit and a small border region dimension upper limit;
• and
• inserting at least one small dummy gate feature pattern in the at least one small border region.

An integrated circuit (IC) comprising:

• a substrate;
• a first intellectual property (IP) block fabricated on the substrate;
• a second IP block fabricated on the substrate;
• a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit;
• and
• at least one small dummy gate feature pattern disposed in the small border region.