Transistor, manufacturing method thereof, and memory

A method for manufacturing a transistor, comprising:

• providing a substrate, wherein the substrate comprises an active area, and a trench penetrating through the active area is provided in the substrate;
• forming a first active layer and a second active layer in the active area, wherein the first active layer and the second active layer are respectively arranged at two sides of the trench;
• forming a channel layer on a bottom and sidewalls of the trench located at the active area, wherein the channel layer comprises a metal oxide semiconductor layer and is in contact with the first active layer and the second active layer;
• and
• forming a gate dielectric layer and a gate in sequence in the trench, wherein the gate dielectric layer covers the channel layer;
• wherein the channel layer comprises a first sub-channel layer and a second sub-channel layer stacked in sequence;
• and the forming the channel layer on the bottom and sidewalls of the trench located at the active area comprises:
• implanting doping ions into the bottom and the sidewalls of the trench located at the active area to form the first sub-channel layer;
• and
• forming the second sub-channel layer covering a bottom and sidewalls of the first sub-channel layer, wherein the second sub-channel layer comprises the metal oxide semiconductor layer;
• wherein the first active layer and the second active layer are located on a top of the first sub-channel layer, and a top of the second sub-channel layer and a top of the first sub-channel layer are flush, and
• wherein the forming the gate dielectric layer in the trench comprises:
• forming the gate dielectric layer in the trench, wherein the gate dielectric layer covers the top of the second sub-channel layer and sidewalls of the first active layer and the second active layer.