Back to results
US 12,757,370 B2Granted
SRAM with staggered stacked FET
AssigneeInternational Business Machines Corporation
InventorsAlbert M. Chu, Carl Radens, Ruilong Xie, Brent A. Anderson, Junli Wang
Life of this patent
Estimating the term…
Abstract
A microelectronic structure including a static random-access memory (SRAM) device that includes a plurality of stacked transistors. Each of the plurality of stacked transistors that includes a bottom transistor and an upper transistor, where the upper transistor is not in vertical alignment with the bottom transistor.
Claims17
A microelectronic structure comprising:
- a static random-access memory (SRAM) device that includes a plurality of stacked transistors;
- and
- wherein the plurality of stacked transistors includes a shared device that includes a bottom transistor and an upper transistor, wherein the upper transistor is not in vertical alignment with the bottom transistor, wherein the plurality of stacked transistors includes an oxide layer located between the upper transistor and the bottom transistor, wherein the shared device includes a shared gate that extends through the oxide layer to connect a plurality of upper channel layers of the upper transistor and a plurality of lower channel layers of the bottom transistor, wherein the plurality of stacked transistors includes a plurality of upper gate cuts and a plurality of lower gate cuts, wherein the upper gate cuts separate gate regions of adjacent upper transistors from each other and the lower gate cuts separate lower gate regions from each other, wherein the plurality of upper gate cuts and the plurality of lower gate cuts are located on different levels;
- wherein the plurality of stacked transistors includes an isolated upper transistor, wherein a gate region of the isolated upper transistor is not connected to a lower gate located in a bottom region of the plurality of stacked transistors, wherein one of the upper gate cuts separates the isolated upper transistor and the shared gate of the shared device, wherein the isolated upper transistor is located on one side of the one upper gate cut and the shared gate is located on a second side of the one upper gate cut.
1 more element
A microelectronic structure comprising:
- a static random-access memory (SRAM) device that includes a plurality of stacked transistors;
- each of the plurality of stacked transistors includes a bottom transistor and an upper transistor, wherein the upper transistor is not in vertical alignment with the bottom transistor;
- a bottom dummy device, wherein the dummy device includes a plurality of nanosheets that extends laterally from a bottom source/drain, wherein an inner spacer is located between the plurality of nanosheets, wherein a gate structure is in contact with at least three different surfaces of each of the plurality of nanosheets and the gate structure contacts the inner spacer, wherein the inner spacer has a first side surface in contact with the bottom source/drain and a second side surface of the inner spacer that is in contact with the gate structure when viewed from a cross section that extends across multiple gate regions of the bottom transistors for the plurality of stacked transistors;
- and
- a shared contact, wherein the shared contact is connected to an upper source/drain of the upper transistor and the bottom source/drain of the bottom transistor, and wherein the shared contact is in direct contact with and extends partially along a surface of a nanosheet of the plurality of nanosheets of the bottom dummy device, wherein the shared contact further directly contacts the gate structure of the bottom dummy device that is in contact with a top surface of the nanosheet of the plurality of nanosheets of the bottom dummy device when viewed from the cross section that extends across multiple gate regions of the bottom transistors for the plurality of stacked transistors.
2 more elements
Dependencies are inferred from the claim text.