Semiconductor memory device and electronic system including the same

A semiconductor memory device comprising:

• a first substrate including a first surface that extends in a first horizontal direction and a second horizontal direction that is orthogonal to the first horizontal direction, and a memory cell region on the first surface;
• and
• a second substrate including a second surface that is below the first substrate, a first peripheral circuit region on the second surface and configured to receive a block selection signal and to transmit a driving signal to the memory cell region,
• wherein the first peripheral circuit region includes a first active region, the first active region including a first gate structure extending in a first direction, a second gate structure extending in a second direction, a third gate structure extending in a third direction, and a first shared drain between the first gate structure, the second gate structure, and the third gate structure, and
• wherein the first direction, the second direction, and the third direction are not parallel to one another and are spaced apart from one another.

An electronic system comprising:

• a main substrate;
• a semiconductor memory device on the main substrate, the semiconductor memory device including a first substrate that includes a peripheral circuit and a second substrate that includes memory cells;
• and
• a controller on the main substrate, the controller being electrically connected to the semiconductor memory device, wherein:
• the semiconductor memory device includes an active region that is defined on the first substrate, the active region includes a first extension extending in a first direction, a second extension extending in a second direction, and a third extension extending in a third direction, the first extension, the second extension, and the third extension forming respective angles greater than 90 degrees relative to one another, the active region includes a pass transistor circuit configured to transmit driving signals such that operating voltages are applied to the memory cells, and
• the pass transistor circuit includes a first gate structure on the first extension, a second gate structure on the second extension, a third gate structure on the third extension, and a shared source/drain between the first gate structure, the second gate structure, and the third gate structure.